Date: Sat, 31 Oct 2020 15:28:21 +0000 (UTC) From: Michal Meloun <mmel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r367210 - stable/12/sys/arm64/rockchip Message-ID: <202010311528.09VFSLEW098473@repo.freebsd.org>
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Author: mmel Date: Sat Oct 31 15:28:21 2020 New Revision: 367210 URL: https://svnweb.freebsd.org/changeset/base/367210 Log: MFC r360293,r360461: r360293: Reorder initialization steps for given pin. If pin is switched from fixed function to GPIO, it should have prepared direction, pull-up/down and default value before function gets switched. Otherwise we may produce unwanted glitch on output pin. Right order of drive strength settings is questionable, but I think that is slightly safer to do it also before function switch. r360461: Multiple fixes for rockchip iodomain driver: - always initialize selector of voltage signaling standard. Various versions of U-boot leaves voltage signaling standard settings for PMUIO2 domain in different state. Always initialize it into expected state. - start the driver as early as possible, the IO domains should be initialized before other drivers are attached. - rename RK3399 register to its name founds in TRM. Modified: stable/12/sys/arm64/rockchip/rk_iodomain.c stable/12/sys/arm64/rockchip/rk_pinctrl.c Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/arm64/rockchip/rk_iodomain.c ============================================================================== --- stable/12/sys/arm64/rockchip/rk_iodomain.c Sat Oct 31 15:27:45 2020 (r367209) +++ stable/12/sys/arm64/rockchip/rk_iodomain.c Sat Oct 31 15:28:21 2020 (r367210) @@ -45,17 +45,20 @@ __FBSDID("$FreeBSD$"); #define RK3288_GRF_IO_VSEL 0x380 #define RK3399_GRF_IO_VSEL 0xe640 -#define RK3399_PMUGRF_IO_VSEL 0x180 +#define RK3399_PMUGRF_SOC_CON0 0x180 struct rk_iodomain_supply { char *name; uint32_t bit; }; +struct rk_iodomain_softc; + struct rk_iodomain_conf { struct rk_iodomain_supply *supply; int nsupply; uint32_t grf_reg; + void (*init)(struct rk_iodomain_softc *sc); }; struct rk_iodomain_softc { @@ -101,10 +104,12 @@ static struct rk_iodomain_supply rk3399_pmu_supply[] = {"pmu1830-supply", 9}, }; +static void rk3399_pmu_init(struct rk_iodomain_softc *sc); static struct rk_iodomain_conf rk3399_pmu_conf = { .supply = rk3399_pmu_supply, .nsupply = nitems(rk3399_pmu_supply), - .grf_reg = RK3399_PMUGRF_IO_VSEL, + .grf_reg = RK3399_PMUGRF_SOC_CON0, + .init = rk3399_pmu_init, }; static struct ofw_compat_data compat_data[] = { @@ -115,6 +120,14 @@ static struct ofw_compat_data compat_data[] = { }; static void +rk3399_pmu_init(struct rk_iodomain_softc *sc) +{ + + SYSCON_WRITE_4(sc->grf, RK3399_PMUGRF_SOC_CON0, + (1 << 8) | (1 << (8 + 16))); /* set pmu1830_volsel */ +} + +static void rk_iodomain_set(struct rk_iodomain_softc *sc) { regulator_t supply; @@ -141,6 +154,8 @@ rk_iodomain_set(struct rk_iodomain_softc *sc) } SYSCON_WRITE_4(sc->grf, sc->conf->grf_reg, reg | mask); + if (sc->conf->init != NULL) + sc->conf->init(sc); } static int @@ -204,4 +219,4 @@ static driver_t rk_iodomain_driver = { static devclass_t rk_iodomain_devclass; EARLY_DRIVER_MODULE(rk_iodomain, simplebus, rk_iodomain_driver, - rk_iodomain_devclass, 0, 0, BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); + rk_iodomain_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); Modified: stable/12/sys/arm64/rockchip/rk_pinctrl.c ============================================================================== --- stable/12/sys/arm64/rockchip/rk_pinctrl.c Sat Oct 31 15:27:45 2020 (r367209) +++ stable/12/sys/arm64/rockchip/rk_pinctrl.c Sat Oct 31 15:28:21 2020 (r367210) @@ -933,7 +933,28 @@ rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, /* Find syscon */ syscon = sc->conf->get_syscon(sc, bank); - /* Parse pin function */ + /* Setup GPIO properties first */ + rv = rk_pinctrl_handle_io(sc, pin_conf, bank, pin); + + /* Then pin pull-up/down */ + bias = sc->conf->parse_bias(pin_conf, bank); + if (bias >= 0) { + reg = sc->conf->get_pd_offset(sc, bank); + reg += bank * 0x10 + ((pin / 8) * 0x4); + bit = (pin % 8) * 2; + mask = (0x3 << bit); + SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); + } + + /* Then drive strength */ + rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®); + if (rv == 0) { + bit = (pin % 8) * 2; + mask = (0x3 << bit); + SYSCON_MODIFY_4(syscon, reg, mask, drive << bit | (mask << 16)); + } + + /* Finally set the pin function */ reg = sc->conf->iomux_conf[i].offset; switch (sc->conf->iomux_conf[i].nbits) { case 4: @@ -967,28 +988,6 @@ rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, * without hi-word write mask. */ SYSCON_MODIFY_4(syscon, reg, mask, function << bit | (mask << 16)); - - /* Pull-Up/Down */ - bias = sc->conf->parse_bias(pin_conf, bank); - if (bias >= 0) { - reg = sc->conf->get_pd_offset(sc, bank); - - reg += bank * 0x10 + ((pin / 8) * 0x4); - bit = (pin % 8) * 2; - mask = (0x3 << bit); - SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); - } - - /* Drive Strength */ - rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®); - if (rv == 0) { - bit = (pin % 8) * 2; - mask = (0x3 << bit); - SYSCON_MODIFY_4(syscon, reg, mask, drive << bit | (mask << 16)); - } - - /* Input/Outpot + default level */ - rv = rk_pinctrl_handle_io(sc, pin_conf, bank, pin); } static int
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