Date: Wed, 21 May 2014 09:26:03 +0000 (UTC) From: Hans Petter Selasky <hselasky@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r266493 - head/sys/dev/usb/controller Message-ID: <201405210926.s4L9Q3hh010322@svn.freebsd.org>
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Author: hselasky Date: Wed May 21 09:26:02 2014 New Revision: 266493 URL: http://svnweb.freebsd.org/changeset/base/266493 Log: - Replace some constants with macros. - Need to set the pre-fetch memory address when reading the host memory. - We currently assume that no endianness conversion is needed. Sponsored by: DARPA, AFRL Modified: head/sys/dev/usb/controller/saf1761_otg.c head/sys/dev/usb/controller/saf1761_otg_reg.h Modified: head/sys/dev/usb/controller/saf1761_otg.c ============================================================================== --- head/sys/dev/usb/controller/saf1761_otg.c Wed May 21 09:19:05 2014 (r266492) +++ head/sys/dev/usb/controller/saf1761_otg.c Wed May 21 09:26:02 2014 (r266493) @@ -253,8 +253,8 @@ saf1761_host_channel_free(struct saf1761 return; /* disable channel */ - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 3), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 0), 0); + SAF1761_WRITE_4(sc, SOTG_PDT(td->channel) + SOTG_PDT_DW3, 0); + SAF1761_WRITE_4(sc, SOTG_PDT(td->channel) + SOTG_PDT_DW0, 0); switch (td->ep_type) { case UE_INTERRUPT: @@ -299,20 +299,25 @@ static uint8_t saf1761_host_setup_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td) { struct usb_device_request req __aligned(4); + uint32_t pdt_addr; uint32_t status; uint32_t count; + uint32_t temp; if (td->channel < SOTG_HOST_CHANNEL_MAX) { - status = SAF1761_READ_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 3)); - if (status & (1 << 31)) { + pdt_addr = SOTG_PDT(td->channel); + + saf1761_read_host_memory_4(sc, pdt_addr + SOTG_PDT_DW3, &status, 1); + + if (status & SOTG_PDT_DW3_ACTIVE) { goto busy; - } else if (status & (1 << 30)) { + } else if (status & SOTG_PDT_DW3_HALTED) { td->error_stall = 1; td->error_any = 1; - } else if (status & (3 << 28)) { + } else if (status & SOTG_PDT_DW3_ERRORS) { td->error_any = 1; } - count = (status & 0x7FFF); + count = (status & SOTG_PDT_DW3_XFER_COUNT); saf1761_host_channel_free(sc, td); goto complete; @@ -332,26 +337,27 @@ saf1761_host_setup_tx(struct saf1761_otg saf1761_write_host_memory_4(sc, SOTG_DATA_ADDR(td->channel), &req, (count + 3) / 4); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 7), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 6), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 5), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 4), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 3), - (1 << 31) | (td->toggle << 25) | (3 << 23)); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 2), - SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8); - - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 1), - td->dw1_value | - (2 << 10) /* SETUP PID */ | - (td->ep_index >> 1)); - - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 0), - (td->ep_index << 31) | - (1 << 29) /* pkt-multiplier */ | + pdt_addr = SOTG_PDT(td->channel); + + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW7, 0); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW6, 0); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW5, 0); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW4, 0); + + temp = SOTG_PDT_DW3_ACTIVE | (td->toggle << 25) | SOTG_PDT_DW3_CERR; + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW3, temp); + + temp = SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8; + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW2, temp); + + temp = td->dw1_value | (2 << 10) /* SETUP PID */ | (td->ep_index >> 1); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW1, temp); + + temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ | (td->max_packet_size << 18) /* wMaxPacketSize */ | (count << 3) /* transfer count */ | - 1 /* valid */); + SOTG_PDT_DW0_VALID; + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW0, temp); td->offset += count; td->remainder -= count; @@ -365,24 +371,29 @@ complete: static uint8_t saf1761_host_bulk_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td) { + uint32_t pdt_addr; + uint32_t temp; + if (td->channel < SOTG_HOST_CHANNEL_MAX) { uint32_t status; uint32_t count; uint8_t got_short; - status = SAF1761_READ_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 3)); + pdt_addr = SOTG_PDT(td->channel); + + saf1761_read_host_memory_4(sc, pdt_addr + SOTG_PDT_DW3, &status, 1); - if (status & (1 << 31)) { + if (status & SOTG_PDT_DW3_ACTIVE) { goto busy; - } else if (status & (1 << 30)) { + } else if (status & SOTG_PDT_DW3_HALTED) { td->error_stall = 1; td->error_any = 1; goto complete; - } else if (status & (3 << 28)) { + } else if (status & SOTG_PDT_DW3_ERRORS) { td->error_any = 1; goto complete; } - count = (status & 0x7FFF); + count = (status & SOTG_PDT_DW3_XFER_COUNT); got_short = 0; /* verify the packet byte count */ @@ -435,26 +446,27 @@ saf1761_host_bulk_data_rx(struct saf1761 /* receive one more packet */ - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 7), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 6), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 5), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 4), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 3), - (1 << 31) | (td->toggle << 25) | (3 << 23)); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 2), - SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8); - - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 1), - td->dw1_value | - (1 << 10) /* IN-PID */ | - (td->ep_index >> 1)); - - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 0), - (td->ep_index << 31) | - (1 << 29) /* pkt-multiplier */ | + pdt_addr = SOTG_PDT(td->channel); + + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW7, 0); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW6, 0); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW5, 0); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW4, 0); + + temp = SOTG_PDT_DW3_ACTIVE | (td->toggle << 25) | SOTG_PDT_DW3_CERR; + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW3, temp); + + temp = SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8; + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW2, temp); + + temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW1, temp); + + temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ | (td->max_packet_size << 18) /* wMaxPacketSize */ | (td->max_packet_size << 3) /* transfer count */ | - 1 /* valid */); + SOTG_PDT_DW0_VALID; + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW0, temp); busy: return (1); /* busy */ complete: @@ -464,18 +476,23 @@ complete: static uint8_t saf1761_host_bulk_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td) { + uint32_t pdt_addr; + uint32_t temp; uint32_t count; if (td->channel < SOTG_HOST_CHANNEL_MAX) { uint32_t status; - status = SAF1761_READ_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 3)); - if (status & (1 << 31)) { + pdt_addr = SOTG_PDT(td->channel); + + saf1761_read_host_memory_4(sc, pdt_addr + SOTG_PDT_DW3, &status, 1); + + if (status & SOTG_PDT_DW3_ACTIVE) { goto busy; - } else if (status & (1 << 30)) { + } else if (status & SOTG_PDT_DW3_HALTED) { td->error_stall = 1; td->error_any = 1; - } else if (status & (3 << 28)) { + } else if (status & SOTG_PDT_DW3_ERRORS) { td->error_any = 1; } @@ -508,26 +525,29 @@ saf1761_host_bulk_data_tx(struct saf1761 td->toggle = 1; } - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 7), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 6), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 5), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 4), 0); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 3), - (1 << 31) | (td->toggle << 25) | (3 << 23)); - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 2), - SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8); - - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 1), - td->dw1_value | - (0 << 10) /* OUT-PID */ | - (td->ep_index >> 1)); - - SAF1761_WRITE_4(sc, SOTG_ISOC_PDT(td->channel) + (4 * 0), - (td->ep_index << 31) | - (1 << 29) /* pkt-multiplier */ | + /* send one more packet */ + + pdt_addr = SOTG_PDT(td->channel); + + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW7, 0); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW6, 0); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW5, 0); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW4, 0); + + temp = SOTG_PDT_DW3_ACTIVE | (td->toggle << 25) | SOTG_PDT_DW3_CERR; + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW3, temp); + + temp = SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8; + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW2, temp); + + temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1); + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW1, temp); + + temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ | (td->max_packet_size << 18) /* wMaxPacketSize */ | (count << 3) /* transfer count */ | - 1 /* valid */); + SOTG_PDT_DW0_VALID; + SAF1761_WRITE_4(sc, pdt_addr + SOTG_PDT_DW0, temp); td->offset += count; td->remainder -= count; Modified: head/sys/dev/usb/controller/saf1761_otg_reg.h ============================================================================== --- head/sys/dev/usb/controller/saf1761_otg_reg.h Wed May 21 09:19:05 2014 (r266492) +++ head/sys/dev/usb/controller/saf1761_otg_reg.h Wed May 21 09:26:02 2014 (r266493) @@ -189,10 +189,25 @@ #define SOTG_PORTSC1_PED (1 << 2) #define SOTG_PORTSC1_ECSC (1 << 1) #define SOTG_PORTSC1_ECCS (1 << 0) +#define SOTG_PDT_DW0 0 +#define SOTG_PDT_DW0_VALID 1U +#define SOTG_PDT_DW1 4 +#define SOTG_PDT_DW2 8 +#define SOTG_PDT_DW3 12 +#define SOTG_PDT_DW3_ACTIVE (1U << 31) +#define SOTG_PDT_DW3_HALTED (1U << 30) +#define SOTG_PDT_DW3_ERRORS (3U << 28) +#define SOTG_PDT_DW3_CERR (3U << 23) +#define SOTG_PDT_DW3_XFER_COUNT 0x7FFF +#define SOTG_PDT_DW4 16 +#define SOTG_PDT_DW5 20 +#define SOTG_PDT_DW6 24 +#define SOTG_PDT_DW7 28 #define SOTG_DATA_ADDR(x) (0x1000 + (512 * (x))) #define SOTG_ASYNC_PDT(x) (0xC00 + ((x) * 32)) #define SOTG_INTR_PDT(x) (0x800 + ((x) * 32)) #define SOTG_ISOC_PDT(x) (0x400 + ((x) * 32)) +#define SOTG_PDT(x) (0x400 + ((x) * 32)) #define SOTG_HC_MEMORY_ADDR(x) (((x) - 0x400) >> 3) #define SOTG_SW_RESET 0x30C #define SOTG_SW_RESET_HC (1 << 1)
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