Date: Mon, 26 Sep 2005 16:11:35 -0400 From: John Baldwin <jhb@FreeBSD.org> To: freebsd-current@freebsd.org Cc: current@freebsd.org, "Wilkinson, Alex" <alex.wilkinson@dsto.defence.gov.au> Subject: Re: Broken MP table detected ... Message-ID: <200509261611.36343.jhb@FreeBSD.org> In-Reply-To: <20050923024615.GT91606@squash.dsto.defence.gov.au> References: <20050920004358.GA76462@squash.dsto.defence.gov.au> <200509211640.38493.jhb@FreeBSD.org> <20050923024615.GT91606@squash.dsto.defence.gov.au>
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On Thursday 22 September 2005 10:46 pm, Wilkinson, Alex wrote: > 0n Wed, Sep 21, 2005 at 04:40:36PM -0400, John Baldwin wrote: > >On Monday 19 September 2005 08:55 pm, Scott Long wrote: > >> Wilkinson, Alex wrote: > >> > Can anyone tell me what the following means, and how to fix it: > >> > > >> > APIC_IO: Testing 8254 interrupt delivery > >> > APIC_IO: Broken MP table detected: 8254 is not connected to > >> > IOAPIC #0 intpin 2 APIC_IO: routing 8254 via 8259 and IOAPIC #0 > >> > intpin 0 > >> > > >> > - aW > >> > >> It means that you need to use 6.0 instead of 5.x =-) It represents > >> the old way that we connected the timecounters, which apparently > >> isn't well supported with newer amd64 boards. 6.0 solves this > >> problem by using a better supported mechanism. > > > >Actually, this is a 4.x method and it basically means that it has > > fallen back to mixed mode for IRQ0. 6.0 certainly does this better. > > 5.x just uses mixed mode by default. > > John, what is mixed mode ? Normally when you use the APICs, you don't use the older 8259A AT-PICs at all. However, the 8259A's are hooked up to pin 0 on the first I/O APIC, so if you enable pin 0 and enable interruput pins on the 8259As, then if they get an interrupt, they will forward it to the first I/O APIC which will then forward it to the CPUs as directed. Using both the old PICs and the APICs at the same time using pin 0 in the first I/O APIC is known as mixed mode. The reason FreeBSD uses it is that some motherboard manufacturers chose to not connect an IRQ0 input from the ISA timer to pin 2 on the first I/O APIC, even though the MP Table said that they did. The reason they could get away with that is that Windows didn't use IRQ0 when it used the APICs, so the motherboards still passed WHQL certification ok (or so I've been told). Linux also doesn't use IRQ0, but uses the built-in countdown periodic timer that each CPU has in its local APIC. In 4.x, the kernel would try to get IRQ0 interrupts via pin 2 on the first I/O APIC and if it didn't work, it printed out the message you saw and enabled mixed mode and enabled IRQ0 in the 8259A AT-PIC. In 5.x, we just always use mixed mode without the runtime test and have a hint for forcing it to not use mixed mode. In 6.x we use the countdown timer in the local APIC like Linux and Windows when using the APICs and don't use IRQ0 at all. -- John Baldwin <jhb@FreeBSD.org> <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" = http://www.FreeBSD.org
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