Date: Sat, 14 Jan 2017 14:43:28 +0100 From: Emmanuel Vadot <manu@bidouilliste.com> To: Zbigniew Bodek <zbb@FreeBSD.org> Cc: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: Re: svn commit: r311455 - head/sys/boot/fdt/dts/arm Message-ID: <20170114144328.1b9e0b3fdfe34b3ae1365798@bidouilliste.com> In-Reply-To: <201701051727.v05HRoup098984@repo.freebsd.org> References: <201701051727.v05HRoup098984@repo.freebsd.org>
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Hello zbb, On Thu, 5 Jan 2017 17:27:50 +0000 (UTC) Zbigniew Bodek <zbb@FreeBSD.org> wrote: > Author: zbb > Date: Thu Jan 5 17:27:50 2017 > New Revision: 311455 > URL: https://svnweb.freebsd.org/changeset/base/311455 > > Log: > Add DTS file for Armada 385 DB-AP board > > Armada38x is already supported in the tree. > This commit adds support for DB-AP board. > File was taken from Linux v4.8 and accustomed to FreeBSD > in minimal possible way. > > Submitted by: Bartosz Szczepanek <bsz@semihalf.com> > Obtained from: Semihalf > Sponsored by: Stormshield > Differential revision: https://reviews.freebsd.org/D7327 > > Added: > head/sys/boot/fdt/dts/arm/armada-385-db-ap.dts (contents, props changed) This file is already present in sys/gnu/dts (from an earlier version of Linux, 4.7-rcX). As I said in the review I'm not sure that we want multiple version of DTS in the tree. Could you use the upstream dts as base (include it in our DTS) and add the FreeBSD needed nodes in it like we do for Allwinner and BeagleBone ? Thanks. > Added: head/sys/boot/fdt/dts/arm/armada-385-db-ap.dts > ============================================================================== > --- /dev/null 00:00:00 1970 (empty, because file is newly added) > +++ head/sys/boot/fdt/dts/arm/armada-385-db-ap.dts Thu Jan 5 17:27:50 2017 (r311455) > @@ -0,0 +1,271 @@ > +/* > + * Device Tree file for Marvell Armada 385 Access Point Development board > + * (DB-88F6820-AP) > + * > + * Copyright (C) 2014 Marvell > + * > + * Nadav Haklai <nadavh@marvell.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without > + * any warranty of any kind, whether express or implied. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + * $FreeBSD$ > + */ > + > +/dts-v1/; > +#include "armada-385.dtsi" > + > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + model = "Marvell Armada 385 Access Point Development Board"; > + compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380"; > + > + chosen { > + stdout-path = "serial1"; > + }; > + > + memory { > + device_type = "memory"; > + reg = <0x00000000 0x80000000>; /* 2GB */ > + }; > + > + soc { > + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; > + > + internal-regs { > + i2c0: i2c@11000 { > + pinctrl-names = "default"; > + pinctrl-0 = <&i2c0_pins>; > + status = "okay"; > + > + /* > + * This bus is wired to two EEPROM > + * sockets, one of which holding the > + * board ID used by the bootloader. > + * Erasing this EEPROM's content will > + * brick the board. > + * Use this bus with caution. > + */ > + }; > + > + mdio@72004 { > + pinctrl-names = "default"; > + pinctrl-0 = <&mdio_pins>; > + > + phy0: ethernet-phy@1 { > + reg = <1>; > + }; > + > + phy1: ethernet-phy@4 { > + reg = <4>; > + }; > + > + phy2: ethernet-phy@6 { > + reg = <6>; > + }; > + }; > + > + /* UART0 is exposed through the JP8 connector */ > + uart0: serial@12000 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_pins>; > + status = "okay"; > + }; > + > + /* > + * UART1 is exposed through a FTDI chip > + * wired to the mini-USB connector > + */ > + uart1: serial@12100 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart1_pins>; > + status = "okay"; > + }; > + > + pinctrl@18000 { > + xhci0_vbus_pins: xhci0-vbus-pins { > + marvell,pins = "mpp44"; > + marvell,function = "gpio"; > + }; > + }; > + > + /* CON3 */ > + ethernet@30000 { > + status = "okay"; > + phy = <&phy2>; > + phy-mode = "sgmii"; > + buffer-manager = <&bm>; > + bm,pool-long = <1>; > + bm,pool-short = <3>; > + }; > + > + /* CON2 */ > + ethernet@34000 { > + status = "okay"; > + phy = <&phy1>; > + phy-mode = "sgmii"; > + buffer-manager = <&bm>; > + bm,pool-long = <2>; > + bm,pool-short = <3>; > + }; > + > + usb@58000 { > + status = "okay"; > + }; > + > + /* CON4 */ > + ethernet@70000 { > + pinctrl-names = "default"; > + > + /* > + * The Reference Clock 0 is used to > + * provide a clock to the PHY > + */ > + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; > + status = "okay"; > + phy = <&phy0>; > + phy-mode = "rgmii-id"; > + buffer-manager = <&bm>; > + bm,pool-long = <0>; > + bm,pool-short = <3>; > + }; > + > + crypto@90000 { > + status = "okay"; > + }; > + > + crypto@92000 { > + status = "okay"; > + }; > + > + bm@c8000 { > + status = "okay"; > + }; > + > + nfc: flash@d0000 { > + status = "okay"; > + num-cs = <1>; > + nand-ecc-strength = <4>; > + nand-ecc-step-size = <512>; > + marvell,nand-keep-config; > + marvell,nand-enable-arbiter; > + nand-on-flash-bbt; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + partition@0 { > + label = "U-Boot"; > + reg = <0x00000000 0x00800000>; > + read-only; > + }; > + > + partition@800000 { > + label = "uImage"; > + reg = <0x00800000 0x00400000>; > + read-only; > + }; > + > + partition@c00000 { > + label = "Root"; > + reg = <0x00c00000 0x3f400000>; > + }; > + }; > + }; > + > + usb3@f0000 { > + status = "okay"; > + usb-phy = <&usb3_phy>; > + }; > + }; > + > + bm-bppi { > + status = "okay"; > + }; > + > + pcie-controller { > + status = "okay"; > + > + /* > + * The three PCIe units are accessible through > + * standard mini-PCIe slots on the board. > + */ > + pcie@1,0 { > + /* Port 0, Lane 0 */ > + status = "okay"; > + }; > + > + pcie@2,0 { > + /* Port 1, Lane 0 */ > + status = "okay"; > + }; > + > + pcie@3,0 { > + /* Port 2, Lane 0 */ > + status = "okay"; > + }; > + }; > + }; > + > + usb3_phy: usb3_phy { > + compatible = "usb-nop-xceiv"; > + vcc-supply = <®_xhci0_vbus>; > + }; > + > + reg_xhci0_vbus: xhci0-vbus { > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&xhci0_vbus_pins>; > + regulator-name = "xhci0-vbus"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + enable-active-high; > + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; > + }; > +}; > + > +&spi1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&spi1_pins>; > + status = "okay"; > + > + spi-flash@0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "st,m25p128", "jedec,spi-nor"; > + reg = <0>; /* Chip select 0 */ > + spi-max-frequency = <54000000>; > + }; > +}; -- Emmanuel Vadot <manu@bidouilliste.com> <manu@freebsd.org>
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