Date: Sat, 7 May 2011 13:08:48 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r221600 - head/sys/dev/ath/ath_hal/ar5416 Message-ID: <201105071308.p47D8miY099695@svn.freebsd.org>
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Author: adrian Date: Sat May 7 13:08:48 2011 New Revision: 221600 URL: http://svn.freebsd.org/changeset/base/221600 Log: Update the ext channel cycpwr threshold 1 register for the extension channel when the channel is HT/40. The new ANI code (primarily for the AR9300/AR9400) in ath9k sets this register but the ANI code for the previous 11n chips didn't set this. Unlike ath9k, only set this for HT/40 channels. Obtained From: ath9k Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c Sat May 7 12:27:25 2011 (r221599) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c Sat May 7 13:08:48 2011 (r221600) @@ -296,6 +296,12 @@ ar5416AniControl(struct ath_hal *ah, HAL } OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]); + + /* Only set the ext channel cycpwr_thr1 field for ht/40 */ + if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) + OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, + AR_PHY_EXT_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]); + if (level > aniState->spurImmunityLevel) ahp->ah_stats.ast_ani_spurup++; else if (level < aniState->spurImmunityLevel) Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h Sat May 7 12:27:25 2011 (r221599) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h Sat May 7 13:08:48 2011 (r221600) @@ -100,6 +100,13 @@ #define AR_PHY_EXT_MINCCA_PWR_S 23 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 #define AR_PHY_EXT_CCA_THRESH62_S 16 +/* + * This duplicates AR_PHY_EXT_CCA_CYCPWR_THR1; it reads more like + * an ANI register this way. + */ +#define AR_PHY_EXT_TIMING5_CYCPWR_THR1 0x0000FE00 +#define AR_PHY_EXT_TIMING5_CYCPWR_THR1_S 9 + #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 #define AR9280_PHY_EXT_MINCCA_PWR_S 16
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