Date: Sat, 7 Sep 2019 11:21:41 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r351980 - in vendor/llvm/dist-release_90: include/llvm/Transforms/Vectorize lib/CodeGen/SelectionDAG lib/Target/PowerPC lib/Target/SystemZ lib/Target/X86 lib/Transforms/Vectorize Message-ID: <201909071121.x87BLfel035791@repo.freebsd.org>
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Author: dim Date: Sat Sep 7 11:21:41 2019 New Revision: 351980 URL: https://svnweb.freebsd.org/changeset/base/351980 Log: Vendor import of llvm release_90 branch r371301: https://llvm.org/svn/llvm-project/llvm/branches/release_90@371301 Modified: vendor/llvm/dist-release_90/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h vendor/llvm/dist-release_90/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp vendor/llvm/dist-release_90/lib/Target/PowerPC/PPCAsmPrinter.cpp vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZInstrInfo.cpp vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZInstrInfo.h vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZLongBranch.cpp vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZMachineScheduler.cpp vendor/llvm/dist-release_90/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist-release_90/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp Modified: vendor/llvm/dist-release_90/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h ============================================================================== --- vendor/llvm/dist-release_90/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h Sat Sep 7 11:19:55 2019 (r351979) +++ vendor/llvm/dist-release_90/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h Sat Sep 7 11:21:41 2019 (r351980) @@ -452,8 +452,8 @@ class LoopVectorizationLegality { (private) /// Holds the widest induction type encountered. Type *WidestIndTy = nullptr; - /// Allowed outside users. This holds the induction and reduction - /// vars which can be accessed from outside the loop. + /// Allowed outside users. This holds the variables that can be accessed from + /// outside the loop. SmallPtrSet<Value *, 4> AllowedExit; /// Can we assume the absence of NaNs. Modified: vendor/llvm/dist-release_90/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp ============================================================================== --- vendor/llvm/dist-release_90/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sat Sep 7 11:19:55 2019 (r351979) +++ vendor/llvm/dist-release_90/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sat Sep 7 11:21:41 2019 (r351980) @@ -1810,7 +1810,7 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I // offsets to its parts don't wrap either. SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, Offsets[i]); - SDValue Val = RetOp.getValue(i); + SDValue Val = RetOp.getValue(RetOp.getResNo() + i); if (MemVTs[i] != ValueVTs[i]) Val = DAG.getPtrExtOrTrunc(Val, getCurSDLoc(), MemVTs[i]); Chains[i] = DAG.getStore(Chain, getCurSDLoc(), Val, Modified: vendor/llvm/dist-release_90/lib/Target/PowerPC/PPCAsmPrinter.cpp ============================================================================== --- vendor/llvm/dist-release_90/lib/Target/PowerPC/PPCAsmPrinter.cpp Sat Sep 7 11:19:55 2019 (r351979) +++ vendor/llvm/dist-release_90/lib/Target/PowerPC/PPCAsmPrinter.cpp Sat Sep 7 11:21:41 2019 (r351980) @@ -866,8 +866,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr const GlobalValue *GValue = MO.getGlobal(); MCSymbol *MOSymbol = getSymbol(GValue); const MCExpr *Exp = - MCSymbolRefExpr::create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL_LO, - OutContext); + MCSymbolRefExpr::create(MOSymbol, + isPPC64 ? MCSymbolRefExpr::VK_PPC_GOT_TPREL_LO + : MCSymbolRefExpr::VK_PPC_GOT_TPREL, + OutContext); TmpInst.getOperand(1) = MCOperand::createExpr(Exp); EmitToStreamer(*OutStreamer, TmpInst); return; Modified: vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZInstrInfo.cpp ============================================================================== --- vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZInstrInfo.cpp Sat Sep 7 11:19:55 2019 (r351979) +++ vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZInstrInfo.cpp Sat Sep 7 11:21:41 2019 (r351980) @@ -468,7 +468,7 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock // Can't handle indirect branches. SystemZII::Branch Branch(getBranchInfo(*I)); - if (!Branch.Target->isMBB()) + if (!Branch.hasMBBTarget()) return true; // Punt on compound branches. @@ -478,7 +478,7 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock if (Branch.CCMask == SystemZ::CCMASK_ANY) { // Handle unconditional branches. if (!AllowModify) { - TBB = Branch.Target->getMBB(); + TBB = Branch.getMBBTarget(); continue; } @@ -490,7 +490,7 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock FBB = nullptr; // Delete the JMP if it's equivalent to a fall-through. - if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) { + if (MBB.isLayoutSuccessor(Branch.getMBBTarget())) { TBB = nullptr; I->eraseFromParent(); I = MBB.end(); @@ -498,7 +498,7 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock } // TBB is used to indicate the unconditinal destination. - TBB = Branch.Target->getMBB(); + TBB = Branch.getMBBTarget(); continue; } @@ -506,7 +506,7 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock if (Cond.empty()) { // FIXME: add X86-style branch swap FBB = TBB; - TBB = Branch.Target->getMBB(); + TBB = Branch.getMBBTarget(); Cond.push_back(MachineOperand::CreateImm(Branch.CCValid)); Cond.push_back(MachineOperand::CreateImm(Branch.CCMask)); continue; @@ -517,7 +517,7 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock // Only handle the case where all conditional branches branch to the same // destination. - if (TBB != Branch.Target->getMBB()) + if (TBB != Branch.getMBBTarget()) return true; // If the conditions are the same, we can leave them alone. @@ -547,7 +547,7 @@ unsigned SystemZInstrInfo::removeBranch(MachineBasicBl continue; if (!I->isBranch()) break; - if (!getBranchInfo(*I).Target->isMBB()) + if (!getBranchInfo(*I).hasMBBTarget()) break; // Remove the branch. I->eraseFromParent(); @@ -1544,6 +1544,10 @@ SystemZInstrInfo::getBranchInfo(const MachineInstr &MI case SystemZ::CLGRJ: return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP, MI.getOperand(2).getImm(), &MI.getOperand(3)); + + case SystemZ::INLINEASM_BR: + // Don't try to analyze asm goto, so pass nullptr as branch target argument. + return SystemZII::Branch(SystemZII::AsmGoto, 0, 0, nullptr); default: llvm_unreachable("Unrecognized branch opcode"); Modified: vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZInstrInfo.h ============================================================================== --- vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZInstrInfo.h Sat Sep 7 11:19:55 2019 (r351979) +++ vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZInstrInfo.h Sat Sep 7 11:21:41 2019 (r351980) @@ -100,11 +100,18 @@ enum BranchType { // An instruction that decrements a 64-bit register and branches if // the result is nonzero. - BranchCTG + BranchCTG, + + // An instruction representing an asm goto statement. + AsmGoto }; // Information about a branch instruction. -struct Branch { +class Branch { + // The target of the branch. In case of INLINEASM_BR, this is nullptr. + const MachineOperand *Target; + +public: // The type of the branch. BranchType Type; @@ -114,12 +121,15 @@ struct Branch { // CCMASK_<N> is set if the branch should be taken when CC == N. unsigned CCMask; - // The target of the branch. - const MachineOperand *Target; - Branch(BranchType type, unsigned ccValid, unsigned ccMask, const MachineOperand *target) - : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {} + : Target(target), Type(type), CCValid(ccValid), CCMask(ccMask) {} + + bool isIndirect() { return Target != nullptr && Target->isReg(); } + bool hasMBBTarget() { return Target != nullptr && Target->isMBB(); } + MachineBasicBlock *getMBBTarget() { + return hasMBBTarget() ? Target->getMBB() : nullptr; + } }; // Kinds of fused compares in compare-and-* instructions. Together with type Modified: vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZLongBranch.cpp ============================================================================== --- vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZLongBranch.cpp Sat Sep 7 11:19:55 2019 (r351979) +++ vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZLongBranch.cpp Sat Sep 7 11:21:41 2019 (r351980) @@ -257,7 +257,7 @@ TerminatorInfo SystemZLongBranch::describeTerminator(M } Terminator.Branch = &MI; Terminator.TargetBlock = - TII->getBranchInfo(MI).Target->getMBB()->getNumber(); + TII->getBranchInfo(MI).getMBBTarget()->getNumber(); } return Terminator; } Modified: vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZMachineScheduler.cpp ============================================================================== --- vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZMachineScheduler.cpp Sat Sep 7 11:19:55 2019 (r351979) +++ vendor/llvm/dist-release_90/lib/Target/SystemZ/SystemZMachineScheduler.cpp Sat Sep 7 11:21:41 2019 (r351980) @@ -108,8 +108,8 @@ void SystemZPostRASchedStrategy::enterMBB(MachineBasic I != SinglePredMBB->end(); I++) { LLVM_DEBUG(dbgs() << "** Emitting incoming branch: "; I->dump();); bool TakenBranch = (I->isBranch() && - (TII->getBranchInfo(*I).Target->isReg() || // Relative branch - TII->getBranchInfo(*I).Target->getMBB() == MBB)); + (TII->getBranchInfo(*I).isIndirect() || + TII->getBranchInfo(*I).getMBBTarget() == MBB)); HazardRec->emitInstruction(&*I, TakenBranch); if (TakenBranch) break; Modified: vendor/llvm/dist-release_90/lib/Target/X86/X86ISelLowering.cpp ============================================================================== --- vendor/llvm/dist-release_90/lib/Target/X86/X86ISelLowering.cpp Sat Sep 7 11:19:55 2019 (r351979) +++ vendor/llvm/dist-release_90/lib/Target/X86/X86ISelLowering.cpp Sat Sep 7 11:21:41 2019 (r351980) @@ -33594,7 +33594,7 @@ static SDValue combineShuffleOfConcatUndef(SDNode *N, } /// Eliminate a redundant shuffle of a horizontal math op. -static SDValue foldShuffleOfHorizOp(SDNode *N) { +static SDValue foldShuffleOfHorizOp(SDNode *N, SelectionDAG &DAG) { unsigned Opcode = N->getOpcode(); if (Opcode != X86ISD::MOVDDUP && Opcode != X86ISD::VBROADCAST) if (Opcode != ISD::VECTOR_SHUFFLE || !N->getOperand(1).isUndef()) @@ -33625,6 +33625,25 @@ static SDValue foldShuffleOfHorizOp(SDNode *N) { HOp.getOperand(0) != HOp.getOperand(1)) return SDValue(); + // The shuffle that we are eliminating may have allowed the horizontal op to + // have an undemanded (undefined) operand. Duplicate the other (defined) + // operand to ensure that the results are defined across all lanes without the + // shuffle. + auto updateHOp = [](SDValue HorizOp, SelectionDAG &DAG) { + SDValue X; + if (HorizOp.getOperand(0).isUndef()) { + assert(!HorizOp.getOperand(1).isUndef() && "Not expecting foldable h-op"); + X = HorizOp.getOperand(1); + } else if (HorizOp.getOperand(1).isUndef()) { + assert(!HorizOp.getOperand(0).isUndef() && "Not expecting foldable h-op"); + X = HorizOp.getOperand(0); + } else { + return HorizOp; + } + return DAG.getNode(HorizOp.getOpcode(), SDLoc(HorizOp), + HorizOp.getValueType(), X, X); + }; + // When the operands of a horizontal math op are identical, the low half of // the result is the same as the high half. If a target shuffle is also // replicating low and high halves, we don't need the shuffle. @@ -33635,7 +33654,7 @@ static SDValue foldShuffleOfHorizOp(SDNode *N) { assert((HOp.getValueType() == MVT::v2f64 || HOp.getValueType() == MVT::v4f64) && HOp.getValueType() == VT && "Unexpected type for h-op"); - return HOp; + return updateHOp(HOp, DAG); } return SDValue(); } @@ -33649,14 +33668,14 @@ static SDValue foldShuffleOfHorizOp(SDNode *N) { (isTargetShuffleEquivalent(Mask, {0, 0}) || isTargetShuffleEquivalent(Mask, {0, 1, 0, 1}) || isTargetShuffleEquivalent(Mask, {0, 1, 2, 3, 0, 1, 2, 3}))) - return HOp; + return updateHOp(HOp, DAG); if (HOp.getValueSizeInBits() == 256 && (isTargetShuffleEquivalent(Mask, {0, 0, 2, 2}) || isTargetShuffleEquivalent(Mask, {0, 1, 0, 1, 4, 5, 4, 5}) || isTargetShuffleEquivalent( Mask, {0, 1, 2, 3, 0, 1, 2, 3, 8, 9, 10, 11, 8, 9, 10, 11}))) - return HOp; + return updateHOp(HOp, DAG); return SDValue(); } @@ -33710,7 +33729,7 @@ static SDValue combineShuffle(SDNode *N, SelectionDAG if (SDValue AddSub = combineShuffleToAddSubOrFMAddSub(N, Subtarget, DAG)) return AddSub; - if (SDValue HAddSub = foldShuffleOfHorizOp(N)) + if (SDValue HAddSub = foldShuffleOfHorizOp(N, DAG)) return HAddSub; } Modified: vendor/llvm/dist-release_90/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp ============================================================================== --- vendor/llvm/dist-release_90/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp Sat Sep 7 11:19:55 2019 (r351979) +++ vendor/llvm/dist-release_90/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp Sat Sep 7 11:21:41 2019 (r351980) @@ -631,6 +631,7 @@ bool LoopVectorizationLegality::canVectorizeInstrs() { // Unsafe cyclic dependencies with header phis are identified during // legalization for reduction, induction and first order // recurrences. + AllowedExit.insert(&I); continue; }
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