Date: Fri, 10 Aug 2018 03:28:40 +0000 (UTC) From: Justin Hibbits <jhibbits@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r337562 - head/sys/powerpc/powerpc Message-ID: <201808100328.w7A3Sebe067471@repo.freebsd.org>
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Author: jhibbits Date: Fri Aug 10 03:28:40 2018 New Revision: 337562 URL: https://svnweb.freebsd.org/changeset/base/337562 Log: powerpc: Add lwsync and ptesync 'sync' opcode variants to ddb disassembler The canonical form of sync is: sync L, E (if Category Elemental Memory Barriers implemented) The L bits (2) denote the type of sync: 0 -- hwsync 1 -- lwsync 2 -- ptesync or hwsync It's been found that most 32-bit CPUs designed prior to the introduction of lwsync will ignore the L bits. However, some cores, particularly the e500 core, will trigger an illegal instruction exception. Adding these variants will make it easier to see which sync variant is actually being used in case of a trap. Modified: head/sys/powerpc/powerpc/db_disasm.c Modified: head/sys/powerpc/powerpc/db_disasm.c ============================================================================== --- head/sys/powerpc/powerpc/db_disasm.c Fri Aug 10 01:43:05 2018 (r337561) +++ head/sys/powerpc/powerpc/db_disasm.c Fri Aug 10 03:28:40 2018 (r337562) @@ -310,7 +310,9 @@ const struct opcode opcodes_1f[] = { { "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B }, { "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR }, { "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB }, - { "sync", 0xfc0007fe, 0x7c0004ac, 0 }, + { "sync", 0xfc6007fe, 0x7c0004ac, 0 }, + { "lwsync", 0xfc6007fe, 0x7c2004ac, 0 }, + { "ptesync", 0xfc6007fe, 0x7c4004ac, 0 }, { "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B }, { "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B }, { "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B },
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