Date: Sat, 23 Feb 2008 22:59:45 GMT From: Rafal Jaworowski <raj@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 136047 for review Message-ID: <200802232259.m1NMxjgB045966@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
http://perforce.freebsd.org/chv.cgi?CH=136047 Change 136047 by raj@raj_mimi on 2008/02/23 22:58:50 On-chip devices are rather part of the SoC, not the CPU core: adjust naming accordingly. Affected files ... .. //depot/projects/e500/sys/powerpc/mpc85xx/lbc.c#2 edit .. //depot/projects/e500/sys/powerpc/mpc85xx/lbc.h#2 edit .. //depot/projects/e500/sys/powerpc/mpc85xx/ocpbus.c#6 edit .. //depot/projects/e500/sys/powerpc/mpc85xx/ocpbus.h#3 edit .. //depot/projects/e500/sys/powerpc/mpc85xx/pci_ocp.c#3 edit Differences ... ==== //depot/projects/e500/sys/powerpc/mpc85xx/lbc.c#2 (text+ko) ==== @@ -95,36 +95,36 @@ * Bus interface definition */ static device_method_t lbc_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, lbc_probe), - DEVMETHOD(device_attach, lbc_attach), - DEVMETHOD(device_shutdown, lbc_shutdown), + /* Device interface */ + DEVMETHOD(device_probe, lbc_probe), + DEVMETHOD(device_attach, lbc_attach), + DEVMETHOD(device_shutdown, lbc_shutdown), - /* Bus interface */ + /* Bus interface */ #if 0 - DEVMETHOD(bus_print_child, lbc_print_child), + DEVMETHOD(bus_print_child, lbc_print_child), #endif - DEVMETHOD(bus_print_child, NULL), - DEVMETHOD(bus_read_ivar, lbc_read_ivar), - DEVMETHOD(bus_setup_intr, NULL), - DEVMETHOD(bus_teardown_intr, NULL), + DEVMETHOD(bus_print_child, NULL), + DEVMETHOD(bus_read_ivar, lbc_read_ivar), + DEVMETHOD(bus_setup_intr, NULL), + DEVMETHOD(bus_teardown_intr, NULL), - DEVMETHOD(bus_get_resource, NULL), - DEVMETHOD(bus_alloc_resource, lbc_alloc_resource), - DEVMETHOD(bus_release_resource, lbc_release_resource), - DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), - DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), + DEVMETHOD(bus_get_resource, NULL), + DEVMETHOD(bus_alloc_resource, lbc_alloc_resource), + DEVMETHOD(bus_release_resource, lbc_release_resource), + DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), + DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), /* local bus CCSR access functions for child */ - DEVMETHOD(lb_write_reg, lbc_write_reg), - DEVMETHOD(lb_read_reg, lbc_read_reg), + DEVMETHOD(lb_write_reg, lbc_write_reg), + DEVMETHOD(lb_read_reg, lbc_read_reg), - { 0, 0 } + { 0, 0 } }; static driver_t lbc_driver = { - "lbc", - lbc_methods, + "lbc", + lbc_methods, sizeof (struct lbc_softc) }; @@ -160,22 +160,18 @@ uint32_t data = 0; switch (bytes) { - case 1: - data = bus_space_read_1(sc->lb_bst, sc->lb_bsh, offset); - - break; - case 2: - data = bus_space_read_2(sc->lb_bst, sc->lb_bsh, offset); - - break; - case 4: - data = bus_space_read_4(sc->lb_bst, sc->lb_bsh, offset); + case 1: + data = bus_space_read_1(sc->lb_bst, sc->lb_bsh, offset); + break; + case 2: + data = bus_space_read_2(sc->lb_bst, sc->lb_bsh, offset); + break; + case 4: + data = bus_space_read_4(sc->lb_bst, sc->lb_bsh, offset); + break; + } - break; - } - return (data); - } static device_t @@ -231,7 +227,7 @@ sc->lb_rid = 0; sc->lb_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->lb_rid, - RF_ACTIVE); + RF_ACTIVE); if (sc->lb_memr == NULL) return (ENXIO); @@ -246,21 +242,21 @@ /* Initialize the LBC registers */ /* Boot Flash */ - LB_WRITE_REG(dev,LBCE500_BR(0), 0xff801001, 4); - LB_WRITE_REG(dev,LBCE500_OR(0), 0xff801040, 4); + LB_WRITE_REG(dev,LBC85XX_BR(0), 0xff801001, 4); + LB_WRITE_REG(dev,LBC85XX_OR(0), 0xff801040, 4); /* SYSPLD */ - LB_WRITE_REG(dev,LBCE500_BR(1), 0xea001001, 4); - LB_WRITE_REG(dev,LBCE500_OR(1), 0xffff1040, 4); + LB_WRITE_REG(dev,LBC85XX_BR(1), 0xea001001, 4); + LB_WRITE_REG(dev,LBC85XX_OR(1), 0xffff1040, 4); #if 0 /* LCD */ - LB_WRITE_REG(dev,LBCE500_BR(2), 0xeb000801, 4); - LB_WRITE_REG(dev,LBCE500_OR(2), 0xffff1100, 4); + LB_WRITE_REG(dev,LBC85XX_BR(2), 0xeb000801, 4); + LB_WRITE_REG(dev,LBC85XX_OR(2), 0xffff1100, 4); #endif - LB_WRITE_REG(dev,LBCE500_LBCR, 0x00000000, 4); - LB_WRITE_REG(dev,LBCE500_LCRR, 0x00030008, 4); + LB_WRITE_REG(dev,LBC85XX_LBCR, 0x00000000, 4); + LB_WRITE_REG(dev,LBC85XX_LCRR, 0x00030008, 4); /* * The unit argument will serve as the bar number. Logic is @@ -277,7 +273,7 @@ rp = &sc->lbc_memregion; rp->rm_type = RMAN_ARRAY; - rp->rm_descr = "MPC8533 Localbus Device Memory"; + rp->rm_descr = "MPC8533 Localbus Device Memory"; /* Not sure below 2 lines are needed */ rp->rm_start = start; rp->rm_end = end; @@ -303,7 +299,7 @@ static int lbc_shutdown(device_t dev) { - return(0); + return(0); } /* @@ -312,7 +308,7 @@ */ static struct resource * lbc_alloc_resource (device_t dev, device_t child, int type, int *rid, - u_long start, u_long end, u_long count, u_int flags) + u_long start, u_long end, u_long count, u_int flags) { struct lbc_softc *sc; struct resource *rv; @@ -338,8 +334,8 @@ #endif rman_set_bustag(rv, &bs_be_tag); rman_set_bushandle(rv, sc->lbc_iomem_va + - rman_get_start(rv) - rp->rm_start); - return (rv); + rman_get_start(rv) - rp->rm_start); + return (rv); } #if 0 @@ -422,8 +418,7 @@ static int lbc_release_resource (device_t dev, device_t child, int type, int rid, - struct resource *res) + struct resource *res) { - return (rman_release_resource(res)); } ==== //depot/projects/e500/sys/powerpc/mpc85xx/lbc.h#2 (text+ko) ==== @@ -36,37 +36,35 @@ #define LBC_DEVTYPE_LCD 1 #define LBC_DEVTYPE_FLASH 2 -#define LB_SDRAM_TYPE 0x01 -#define LB_GPCM_TYPE 0x02 -#define LB_UPM_TYPE 0x04 +#define LB_SDRAM_TYPE 0x01 +#define LB_GPCM_TYPE 0x02 +#define LB_UPM_TYPE 0x04 -#define LBCE500_START (0x5000) -#define LBCE500_SIZE 0x1000 -#define LBCE500_END (LBCE500_START + LBCE500_SIZE) - +#define LBC85XX_START (0x5000) +#define LBC85XX_SIZE 0x1000 +#define LBC85XX_END (LBC85XX_START + LBC85XX_SIZE) /* * Local access registers. */ -#define LBCE500_BR(n) (LBCE500_START + (8 * n)) /* Base Registers */ -#define LBCE500_OR(n) (LBCE500_START + 4 + (8 * n)) /* Options Registers */ +#define LBC85XX_BR(n) (LBC85XX_START + (8 * n)) /* Base Registers */ +#define LBC85XX_OR(n) (LBC85XX_START + 4 + (8 * n)) /* Options Registers */ -#define LBCE500_MAR (LBCE500_START + 0x68) -#define LBCE500_MAMR (LBCE500_START + 0x70) -#define LBCE500_MBMR (LBCE500_START + 0x74) -#define LBCE500_MCMR (LBCE500_START + 0x78) -#define LBCE500_MRTPR (LBCE500_START + 0x84) -#define LBCE500_MDR (LBCE500_START + 0x88) -#define LBCE500_LSDMR (LBCE500_START + 0x94) -#define LBCE500_LURT (LBCE500_START + 0xA0) -#define LBCE500_LSRT (LBCE500_START + 0xA4) -#define LBCE500_LTESR (LBCE500_START + 0xB0) -#define LBCE500_LTEDR (LBCE500_START + 0xB4) -#define LBCE500_LTEIR (LBCE500_START + 0xB8) -#define LBCE500_LTEATR (LBCE500_START + 0xBC) -#define LBCE500_LTEAR (LBCE500_START + 0xC0) -#define LBCE500_LBCR (LBCE500_START + 0xD0) -#define LBCE500_LCRR (LBCE500_START + 0xD4) - +#define LBC85XX_MAR (LBC85XX_START + 0x68) +#define LBC85XX_MAMR (LBC85XX_START + 0x70) +#define LBC85XX_MBMR (LBC85XX_START + 0x74) +#define LBC85XX_MCMR (LBC85XX_START + 0x78) +#define LBC85XX_MRTPR (LBC85XX_START + 0x84) +#define LBC85XX_MDR (LBC85XX_START + 0x88) +#define LBC85XX_LSDMR (LBC85XX_START + 0x94) +#define LBC85XX_LURT (LBC85XX_START + 0xA0) +#define LBC85XX_LSRT (LBC85XX_START + 0xA4) +#define LBC85XX_LTESR (LBC85XX_START + 0xB0) +#define LBC85XX_LTEDR (LBC85XX_START + 0xB4) +#define LBC85XX_LTEIR (LBC85XX_START + 0xB8) +#define LBC85XX_LTEATR (LBC85XX_START + 0xBC) +#define LBC85XX_LTEAR (LBC85XX_START + 0xC0) +#define LBC85XX_LBCR (LBC85XX_START + 0xD0) +#define LBC85XX_LCRR (LBC85XX_START + 0xD4) #endif /* _MACHINE_LOCALBUS_H */ ==== //depot/projects/e500/sys/powerpc/mpc85xx/ocpbus.c#6 (text+ko) ==== @@ -138,15 +138,15 @@ switch (type) { case SYS_RES_MEMORY: switch (trgt) { - case OCPE500_TGTIF_PCI0: + case OCP85XX_TGTIF_PCI0: addr = 0x80000000; size = 0x10000000; break; - case OCPE500_TGTIF_PCI1: + case OCP85XX_TGTIF_PCI1: addr = 0x90000000; size = 0x10000000; break; - case OCPE500_TGTIF_PCI2: + case OCP85XX_TGTIF_PCI2: addr = 0xA0000000; size = 0x10000000; break; @@ -156,15 +156,15 @@ break; case SYS_RES_IOPORT: switch (trgt) { - case OCPE500_TGTIF_PCI0: + case OCP85XX_TGTIF_PCI0: addr = 0xff000000; size = 0x00010000; break; - case OCPE500_TGTIF_PCI1: + case OCP85XX_TGTIF_PCI1: addr = 0xff010000; size = 0x00010000; break; - case OCPE500_TGTIF_PCI2: + case OCP85XX_TGTIF_PCI2: addr = 0xff020000; size = 0x00010000; break; @@ -185,21 +185,21 @@ /* Check if already programmed. */ for (i = 0; i < 8; i++) { - if (sr == in32(OCPE500_LAWSR(i)) && - bar == in32(OCPE500_LAWBAR(i))) + if (sr == in32(OCP85XX_LAWSR(i)) && + bar == in32(OCP85XX_LAWBAR(i))) return (0); } /* Find an unused access window .*/ for (i = 0; i < 8; i++) { - if ((in32(OCPE500_LAWSR(i)) & 0x80000000) == 0) + if ((in32(OCP85XX_LAWSR(i)) & 0x80000000) == 0) break; } if (i == 8) return (ENOSPC); - out32(OCPE500_LAWBAR(i), bar); - out32(OCPE500_LAWSR(i), sr); + out32(OCP85XX_LAWBAR(i), bar); + out32(OCP85XX_LAWSR(i), sr); return (0); } @@ -267,16 +267,16 @@ /* Clear local access windows. */ for (i = 0; i < 8; i++) { - sr = in32(OCPE500_LAWSR(i)); + sr = in32(OCP85XX_LAWSR(i)); if ((sr & 0x80000000) == 0) continue; if ((sr & 0x00f00000) == 0x00f00000) continue; - out32(OCPE500_LAWSR(i), sr & 0x7fffffff); + out32(OCP85XX_LAWSR(i), sr & 0x7fffffff); } device_printf(dev, "PORDEVSR=%08x, PORDEVSR2=%08x\n", - in32(OCPE500_PORDEVSR), in32(OCPE500_PORDEVSR2)); + in32(OCP85XX_PORDEVSR), in32(OCP85XX_PORDEVSR2)); return (bus_generic_attach(dev)); } @@ -297,63 +297,63 @@ }; const struct ocp_resource mpc8555_resources[] = { - {OCPBUS_DEVTYPE_PIC, 0, SYS_RES_MEMORY, 0, OCPE500_OPENPIC_OFF, - OCPE500_OPENPIC_SIZE}, + {OCPBUS_DEVTYPE_PIC, 0, SYS_RES_MEMORY, 0, OCP85XX_OPENPIC_OFF, + OCP85XX_OPENPIC_SIZE}, - {OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_MEMORY, 0, OCPE500_QUICC_OFF, - OCPE500_QUICC_SIZE}, + {OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_MEMORY, 0, OCP85XX_QUICC_OFF, + OCP85XX_QUICC_SIZE}, {OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(30), 1}, - {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_MEMORY, 0, OCPE500_TSEC0_OFF, - OCPE500_TSEC_SIZE}, + {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_MEMORY, 0, OCP85XX_TSEC0_OFF, + OCP85XX_TSEC_SIZE}, {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(13), 1}, {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 1, PIC_IRQ_INT(14), 1}, {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 2, PIC_IRQ_INT(18), 1}, - {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_MEMORY, 0, OCPE500_TSEC1_OFF, - OCPE500_TSEC_SIZE}, + {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_MEMORY, 0, OCP85XX_TSEC1_OFF, + OCP85XX_TSEC_SIZE}, {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(19), 1}, {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 1, PIC_IRQ_INT(20), 1}, {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 2, PIC_IRQ_INT(24), 1}, - {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_MEMORY, 0, OCPE500_TSEC2_OFF, - OCPE500_TSEC_SIZE}, + {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_MEMORY, 0, OCP85XX_TSEC2_OFF, + OCP85XX_TSEC_SIZE}, {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 0, PIC_IRQ_INT(15), 1}, {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 1, PIC_IRQ_INT(16), 1}, {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 2, PIC_IRQ_INT(17), 1}, - {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_MEMORY, 0, OCPE500_TSEC3_OFF, - OCPE500_TSEC_SIZE}, + {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_MEMORY, 0, OCP85XX_TSEC3_OFF, + OCP85XX_TSEC_SIZE}, {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 0, PIC_IRQ_INT(21), 1}, {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 1, PIC_IRQ_INT(22), 1}, {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 2, PIC_IRQ_INT(23), 1}, - {OCPBUS_DEVTYPE_UART, 0, SYS_RES_MEMORY, 0, OCPE500_UART0_OFF, - OCPE500_UART_SIZE}, + {OCPBUS_DEVTYPE_UART, 0, SYS_RES_MEMORY, 0, OCP85XX_UART0_OFF, + OCP85XX_UART_SIZE}, {OCPBUS_DEVTYPE_UART, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(26), 1}, - {OCPBUS_DEVTYPE_UART, 1, SYS_RES_MEMORY, 0, OCPE500_UART1_OFF, - OCPE500_UART_SIZE}, + {OCPBUS_DEVTYPE_UART, 1, SYS_RES_MEMORY, 0, OCP85XX_UART1_OFF, + OCP85XX_UART_SIZE}, {OCPBUS_DEVTYPE_UART, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(26), 1}, - {OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_MEMORY, 0, OCPE500_PCI0_OFF, - OCPE500_PCI_SIZE}, - {OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_MEMORY, 1, 0, OCPE500_TGTIF_PCI0}, - {OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_IOPORT, 1, 0, OCPE500_TGTIF_PCI0}, - {OCPBUS_DEVTYPE_PCIB, 1, SYS_RES_MEMORY, 0, OCPE500_PCI1_OFF, - OCPE500_PCI_SIZE}, - {OCPBUS_DEVTYPE_PCIB, 1, SYS_RES_MEMORY, 1, 0, OCPE500_TGTIF_PCI1}, - {OCPBUS_DEVTYPE_PCIB, 1, SYS_RES_IOPORT, 1, 0, OCPE500_TGTIF_PCI1}, - {OCPBUS_DEVTYPE_PCIB, 2, SYS_RES_MEMORY, 0, OCPE500_PCI2_OFF, - OCPE500_PCI_SIZE}, - {OCPBUS_DEVTYPE_PCIB, 2, SYS_RES_MEMORY, 1, 0, OCPE500_TGTIF_PCI2}, - {OCPBUS_DEVTYPE_PCIB, 2, SYS_RES_IOPORT, 1, 0, OCPE500_TGTIF_PCI2}, + {OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_MEMORY, 0, OCP85XX_PCI0_OFF, + OCP85XX_PCI_SIZE}, + {OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_MEMORY, 1, 0, OCP85XX_TGTIF_PCI0}, + {OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_IOPORT, 1, 0, OCP85XX_TGTIF_PCI0}, + {OCPBUS_DEVTYPE_PCIB, 1, SYS_RES_MEMORY, 0, OCP85XX_PCI1_OFF, + OCP85XX_PCI_SIZE}, + {OCPBUS_DEVTYPE_PCIB, 1, SYS_RES_MEMORY, 1, 0, OCP85XX_TGTIF_PCI1}, + {OCPBUS_DEVTYPE_PCIB, 1, SYS_RES_IOPORT, 1, 0, OCP85XX_TGTIF_PCI1}, + {OCPBUS_DEVTYPE_PCIB, 2, SYS_RES_MEMORY, 0, OCP85XX_PCI2_OFF, + OCP85XX_PCI_SIZE}, + {OCPBUS_DEVTYPE_PCIB, 2, SYS_RES_MEMORY, 1, 0, OCP85XX_TGTIF_PCI2}, + {OCPBUS_DEVTYPE_PCIB, 2, SYS_RES_IOPORT, 1, 0, OCP85XX_TGTIF_PCI2}, - {OCPBUS_DEVTYPE_LBC, 0, SYS_RES_MEMORY, 0, OCPE500_LBC_OFF, - OCPE500_LBC_SIZE}, - {OCPBUS_DEVTYPE_LBC, 0, SYS_RES_MEMORY, 1, 0, OCPE500_TGTIF_LBC}, + {OCPBUS_DEVTYPE_LBC, 0, SYS_RES_MEMORY, 0, OCP85XX_LBC_OFF, + OCP85XX_LBC_SIZE}, + {OCPBUS_DEVTYPE_LBC, 0, SYS_RES_MEMORY, 1, 0, OCP85XX_TGTIF_LBC}, - {OCPBUS_DEVTYPE_I2C, 0, SYS_RES_MEMORY, 0, OCPE500_I2C0_OFF, - OCPE500_I2C_SIZE}, + {OCPBUS_DEVTYPE_I2C, 0, SYS_RES_MEMORY, 0, OCP85XX_I2C0_OFF, + OCP85XX_I2C_SIZE}, {OCPBUS_DEVTYPE_I2C, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(27), 1}, - {OCPBUS_DEVTYPE_I2C, 1, SYS_RES_MEMORY, 0, OCPE500_I2C1_OFF, - OCPE500_I2C_SIZE}, + {OCPBUS_DEVTYPE_I2C, 1, SYS_RES_MEMORY, 0, OCP85XX_I2C1_OFF, + OCP85XX_I2C_SIZE}, {OCPBUS_DEVTYPE_I2C, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(27), 1}, {0} ==== //depot/projects/e500/sys/powerpc/mpc85xx/ocpbus.h#3 (text+ko) ==== @@ -25,51 +25,51 @@ * SUCH DAMAGE. * */ -#ifndef _MACHINE_OCPE500_H_ -#define _MACHINE_OCPE500_H_ +#ifndef _MACHINE_OCP85XX_H_ +#define _MACHINE_OCP85XX_H_ /* * Local access registers. */ -#define OCPE500_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x20 * (n)) -#define OCPE500_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x20 * (n)) +#define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x20 * (n)) +#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x20 * (n)) /* * Power-On Reset configuration. */ -#define OCPE500_PORDEVSR (CCSRBAR_VA + 0xe000c) -#define OCPE500_PORDEVSR2 (CCSRBAR_VA + 0xe0014) +#define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c) +#define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014) /* * OCP Bus Definitions */ -#define OCPE500_I2C0_OFF 0x03000 -#define OCPE500_I2C1_OFF 0x03100 -#define OCPE500_I2C_SIZE 0x15 -#define OCPE500_UART0_OFF 0x04500 -#define OCPE500_UART1_OFF 0x04600 -#define OCPE500_UART_SIZE 0x10 -#define OCPE500_LBC_OFF 0x05000 -#define OCPE500_LBC_SIZE 0x1000 -#define OCPE500_PCI0_OFF 0x08000 -#define OCPE500_PCI1_OFF 0x09000 -#define OCPE500_PCI2_OFF 0x0A000 -#define OCPE500_PCI_SIZE 0x1000 -#define OCPE500_TSEC0_OFF 0x24000 -#define OCPE500_TSEC1_OFF 0x25000 -#define OCPE500_TSEC2_OFF 0x26000 -#define OCPE500_TSEC3_OFF 0x27000 -#define OCPE500_TSEC_SIZE 0x1000 -#define OCPE500_OPENPIC_OFF 0x40000 -#define OCPE500_OPENPIC_SIZE 0x200B4 -#define OCPE500_QUICC_OFF 0x80000 -#define OCPE500_QUICC_SIZE 0x20000 +#define OCP85XX_I2C0_OFF 0x03000 +#define OCP85XX_I2C1_OFF 0x03100 +#define OCP85XX_I2C_SIZE 0x15 +#define OCP85XX_UART0_OFF 0x04500 +#define OCP85XX_UART1_OFF 0x04600 +#define OCP85XX_UART_SIZE 0x10 +#define OCP85XX_LBC_OFF 0x05000 +#define OCP85XX_LBC_SIZE 0x1000 +#define OCP85XX_PCI0_OFF 0x08000 +#define OCP85XX_PCI1_OFF 0x09000 +#define OCP85XX_PCI2_OFF 0x0A000 +#define OCP85XX_PCI_SIZE 0x1000 +#define OCP85XX_TSEC0_OFF 0x24000 +#define OCP85XX_TSEC1_OFF 0x25000 +#define OCP85XX_TSEC2_OFF 0x26000 +#define OCP85XX_TSEC3_OFF 0x27000 +#define OCP85XX_TSEC_SIZE 0x1000 +#define OCP85XX_OPENPIC_OFF 0x40000 +#define OCP85XX_OPENPIC_SIZE 0x200B4 +#define OCP85XX_QUICC_OFF 0x80000 +#define OCP85XX_QUICC_SIZE 0x20000 -#define OCPE500_TGTIF_PCI0 0 -#define OCPE500_TGTIF_PCI1 1 -#define OCPE500_TGTIF_PCI2 2 -#define OCPE500_TGTIF_LBC 4 -#define OCPE500_TGTIF_RAM 15 +#define OCP85XX_TGTIF_PCI0 0 +#define OCP85XX_TGTIF_PCI1 1 +#define OCP85XX_TGTIF_PCI2 2 +#define OCP85XX_TGTIF_LBC 4 +#define OCP85XX_TGTIF_RAM 15 /* * PIC definitions @@ -81,4 +81,4 @@ #define PIC_IRQ_EXT(n) (PIC_IRQ_START + (n)) #define PIC_IRQ_INT(n) (PIC_IRQ_START + 16 + (n)) -#endif /* _MACHINE_OCPE500_H */ +#endif /* _MACHINE_OCP85XX_H */ ==== //depot/projects/e500/sys/powerpc/mpc85xx/pci_ocp.c#3 (text+ko) ==== @@ -568,7 +568,7 @@ KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); switch (tgt) { - case OCPE500_TGTIF_RAM: + case OCP85XX_TGTIF_RAM: attr = 0xa0f55000 | (ffsl(size) - 2); break; default: @@ -668,7 +668,7 @@ struct pci_ocp_softc *sc; uint32_t cfgreg; int error; - + sc = device_get_softc(dev); sc->sc_dev = dev; @@ -695,14 +695,14 @@ pci_ocp_inbound(sc, 1, -1, 0, 0, 0); pci_ocp_inbound(sc, 2, -1, 0, 0, 0); - pci_ocp_inbound(sc, 3, OCPE500_TGTIF_RAM, 0, 2U*1024U*1024U*1024U, 0); + pci_ocp_inbound(sc, 3, OCP85XX_TGTIF_RAM, 0, 2U*1024U*1024U*1024U, 0); sc->sc_busnr = pci_ocp_busnr; pci_ocp_init(sc, sc->sc_busnr); pci_ocp_busnr++; - device_add_child(dev, "pci", -1); - return (bus_generic_attach(dev)); + device_add_child(dev, "pci", -1); + return (bus_generic_attach(dev)); } static struct resource * @@ -750,7 +750,6 @@ pci_ocp_release_resource(device_t dev, device_t child, int type, int rid, struct resource *res) { - return (rman_release_resource(res)); }
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200802232259.m1NMxjgB045966>