Date: Sun, 05 Oct 2008 10:50:26 +0200 From: Goran Lowkrantz <glz@hidden-powers.com> To: "Andrey V. Elsukov" <bu7cher@yandex.ru>, freebsd-stable@freebsd.org Cc: kib@freebsd.org, sos@freebsd.org Subject: Re: Request for testing: ata(4) MFC Message-ID: <DBC025D285DB55145A1D446D@[10.255.253.2]> In-Reply-To: <676151223134689@webmail38.yandex.ru> References: <676151223134689@webmail38.yandex.ru>
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[-- Attachment #1 --]
--On Saturday, October 04, 2008 19:38 +0400 "Andrey V. Elsukov"
<bu7cher@yandex.ru> wrote:
> Hi, All.
>
> I prepared patch to make MFC of ata(4) driver into RELENG_7
> before 7.1-RELEASE. Depending on results of the testing patch
> will be commited or not (if some regressions will be detected).
> So if you want or just can test it, please try and report here.
>
Installed and tested with no ill effects on an ASUS M2N-VM DVI board. Still
need to manually apply the attached patch, picked up on the list a while
ago, to have the built-in SATA controller detected and recognized as AHCI
capable.
Cheers,
Goran
Attachments:
lspci output of controller under test.
original patch for controller.
updated patch against tested patchset.
---
"There is hopeful symbolism in the fact that flags do not wave in a vacuum."
-- Arthur C. Clarke
[-- Attachment #2 --]
00:09.0 SATA controller [0106]: nVidia Corporation MCP67 AHCI Controller [10de:0554] (rev a2) (prog-if 01 [AHCI 1.0])
Subsystem: ASUSTeK Computer Inc. Unknown device [1043:82b3]
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0 (750ns min, 250ns max)
Interrupt: pin A routed to IRQ 22
Region 0: I/O ports at c480
Region 1: I/O ports at c400
Region 2: I/O ports at c080
Region 3: I/O ports at c000
Region 4: I/O ports at bc00
Region 5: Memory at f9ef6000 (32-bit, non-prefetchable)
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [8c] SATA HBA <?>
[-- Attachment #3 --]
Index: src/sys/dev/ata/ata-chipset.c
===================================================================
RCS file: /ncvs/src/sys/dev/ata/ata-chipset.c,v
retrieving revision 1.225
diff -u -p -r1.225 ata-chipset.c
--- src/sys/dev/ata/ata-chipset.c 15 Aug 2008 10:55:11 -0000 1.225
+++ src/sys/dev/ata/ata-chipset.c 23 Sep 2008 05:06:28 -0000
@@ -3372,7 +3372,9 @@ ata_nvidia_ident(device_t dev)
{ ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
{ ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" },
{ ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" },
+ { ATA_NFORCE_MCP67_A1, 0, 0, NVAHCI, ATA_SA300, "nForce MCP67" },
{ ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" },
+ { ATA_NFORCE_MCP73_A1, 0, 0, NVAHCI, ATA_SA300, "nForce MCP73" },
{ ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" },
{ 0, 0, 0, 0, 0, 0}} ;
@@ -3380,7 +3382,12 @@ ata_nvidia_ident(device_t dev)
return ENXIO;
ata_set_desc(dev);
- ctlr->chipinit = ata_nvidia_chipinit;
+
+ if (ctlr->chip->cfg2 == NVAHCI)
+ ctlr->chipinit = ata_ahci_chipinit;
+ else
+ ctlr->chipinit = ata_nvidia_chipinit;
+
return 0;
}
Index: src/sys/dev/ata/ata-pci.h
===================================================================
RCS file: /ncvs/src/sys/dev/ata/ata-pci.h,v
retrieving revision 1.89
diff -u -p -r1.89 ata-pci.h
--- src/sys/dev/ata/ata-pci.h 10 Jul 2008 21:36:53 -0000 1.89
+++ src/sys/dev/ata/ata-pci.h 23 Sep 2008 05:06:28 -0000
@@ -243,8 +243,10 @@ struct ata_connect_task {
#define ATA_NFORCE_MCP61_S2 0x03f610de
#define ATA_NFORCE_MCP61_S3 0x03f710de
#define ATA_NFORCE_MCP65 0x044810de
+#define ATA_NFORCE_MCP67_A1 0x055010de
#define ATA_NFORCE_MCP67 0x056010de
#define ATA_NFORCE_MCP73 0x056c10de
+#define ATA_NFORCE_MCP73_A1 0x07f810de
#define ATA_NFORCE_MCP77 0x075910de
#define ATA_PROMISE_ID 0x105a
@@ -450,6 +452,7 @@ struct ata_connect_task {
#define NVIDIA 0x0004
#define NV4 0x0010
#define NVQ 0x0020
+#define NVAHCI 0x0040
#define VIACLK 0x0100
#define VIABUG 0x0200
#define VIABAR 0x0400
[-- Attachment #4 --]
--- src/sys/dev/ata/ata-chipset.c.orig 2008-10-05 10:43:37.704572883 +0200
+++ src/sys/dev/ata/ata-chipset.c 2008-10-05 10:44:14.193066654 +0200
@@ -3495,7 +3495,9 @@
{ ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
{ ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" },
{ ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" },
+ { ATA_NFORCE_MCP67_A2, 0, 0, NVAHCI, ATA_SA300, "nForce MCP67" },
{ ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" },
+ { ATA_NFORCE_MCP73_A1, 0, 0, NVAHCI, ATA_SA300, "nForce MCP73" },
{ ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" },
{ 0, 0, 0, 0, 0, 0}} ;
@@ -3504,7 +3506,10 @@
ata_set_desc(dev);
- ctlr->chipinit = ata_nvidia_chipinit;
+ if (ctlr->chip->cfg2 == NVAHCI)
+ ctlr->chipinit = ata_ahci_chipinit;
+ else
+ ctlr->chipinit = ata_nvidia_chipinit;
return 0;
}
--- src/sys/dev/ata/ata-pci.h.orig 2008-10-05 10:40:51.398323976 +0200
+++ src/sys/dev/ata/ata-pci.h 2008-10-05 10:45:25.647032967 +0200
@@ -246,8 +246,10 @@
#define ATA_NFORCE_MCP61_S2 0x03f610de
#define ATA_NFORCE_MCP61_S3 0x03f710de
#define ATA_NFORCE_MCP65 0x044810de
+#define ATA_NFORCE_MCP67_A2 0x055010de
#define ATA_NFORCE_MCP67 0x056010de
#define ATA_NFORCE_MCP73 0x056c10de
+#define ATA_NFORCE_MCP73_A1 0x07f810de
#define ATA_NFORCE_MCP77 0x075910de
#define ATA_PROMISE_ID 0x105a
@@ -454,6 +456,7 @@
#define NVIDIA 0x0004
#define NV4 0x0010
#define NVQ 0x0020
+#define NVAHCI 0x0040
#define VIACLK 0x0100
#define VIABUG 0x0200
#define VIABAR 0x0400
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