Date: Thu, 14 Jun 2018 07:53:55 +0200 From: Emmanuel Vadot <manu@bidouilliste.com> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: Re: svn commit: r335108 - head/sys/arm64/rockchip/clk Message-ID: <20180614075355.39845fb56979c7226692c3f9@bidouilliste.com> In-Reply-To: <201806140543.w5E5hjS8036518@repo.freebsd.org> References: <201806140543.w5E5hjS8036518@repo.freebsd.org>
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On Thu, 14 Jun 2018 05:43:45 +0000 (UTC) Emmanuel Vadot <manu@FreeBSD.org> wrote: > Author: manu > Date: Thu Jun 14 05:43:45 2018 > New Revision: 335108 > URL: https://svnweb.freebsd.org/changeset/base/335108 > > Log: > rk_pll: Add support for mode > > RockChip PLL have two modes controlled by a register, a "slow mode" (the > default one) where the frequency is derived from the 24Mhz oscillator on the > board, and a "normal" one when the pll take it's input from the real PLL output. > > Default the mode to normal for all the PLLs. > Thanks to jmcneill@ for the tip by the way. -- Emmanuel Vadot <manu@bidouilliste.com> <manu@freebsd.org>
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