Date: Thu, 6 May 2004 14:47:14 -0400 From: John Baldwin <jhb@FreeBSD.org> To: freebsd-current@FreeBSD.org Cc: current@FreeBSD.org Subject: Re: 4.7 vs 5.2.1 SMP/UP bridging performance Message-ID: <200405061447.14406.jhb@FreeBSD.org> In-Reply-To: <16538.33610.967480.120194@grasshopper.cs.duke.edu> References: <FE045D4D9F7AED4CBFF1B3B813C85337021AB38C@mail.sandvine.com> <200405061411.27216.jhb@FreeBSD.org> <16538.33610.967480.120194@grasshopper.cs.duke.edu>
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On Thursday 06 May 2004 02:26 pm, Andrew Gallatin wrote: > John Baldwin writes: > > and lfence is only on PIV+. I don't recall when mfence first appeared.. > > perhaps PII? If the lock is really expensive, then perhaps we could > > make atomic_cmpset() be actual functions (ugh) rather than inlines that > > did a branch to use foofence for PIV rather than the default. The > > branches would suck, but it might be faster than the lock. Of course, > > this would greatly pessimize non-PIV. > > According to http://www.sandpile.org/ia32/coherent.htm, > both mfence and lfence require SSE2, so sfence has the broadest > coverage. > > But since only P4 needs it, and since lfence is ~25% cheaper, maybe > there should be a separate config option for it, and it should be a > straight conditional compile option for those of us cursed w/P4s. That could work I guess. Just can't stick it in GENERIC. options INTEL_MADE_MY_PIV_A_TORTOISE or some such. :) -- John Baldwin <jhb@FreeBSD.org> <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" = http://www.FreeBSD.org
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