Date: Thu, 28 Apr 2005 18:29:31 +1000 From: Peter Jeremy <PeterJeremy@optushome.com.au> To: /dev/null <null@dnswatch.com> Cc: freebsd-current@freebsd.org Subject: Re: can't build kernel [with CONFIG this time][[[FIXED]]] Message-ID: <20050428082931.GA232@cirb503493.alcatel.com.au> In-Reply-To: <59642.216.177.243.35.1114655240.localmail@webmail.dnswatch.com> References: <61364.216.177.243.42.1114593685.localmail@webmail.dnswatch.com> <84dead7205042706554f32484@mail.gmail.com> <57775.216.177.243.35.1114633009.localmail@webmail.dnswatch.com> <20050427204939.GA796@uk.tiscali.com> <53015.216.177.243.35.1114635611.localmail@webmail.dnswatch.com> <20050427212835.GA87673@uk.tiscali.com> <64018.216.177.243.35.1114641057.localmail@webmail.dnswatch.com> <42701D35.6020307@gmail.com> <42703671.8060707@attglobal.net> <59642.216.177.243.35.1114655240.localmail@webmail.dnswatch.com>
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On Wed, 2005-Apr-27 19:27:20 -0700, /dev/null wrote: >In my case I think it was just "sync" issues between the CPU cache and >the RAM. Although it could have been just that this processor drove >the RAM stick hard enough to make it fail. No matter, the stick of RAM is >working flawlessly in a different box. :) Modern hardware is pushed very close to the limits. Maybe the RAM has some pattern sensitivity that just happens to be hit by buildkernel or buildworld. Maybe a combination of marginal bypass capacitors, marginal memory bus drivers means that the logic transition is a few picoseconds longer than desirable if a large number of bits change state simultaneously so that the transition isn't seen by the marginal receiver. -- Peter Jeremy
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