Date: Sun, 20 Feb 2000 00:45:01 -0800 From: Arun Sharma <adsharma@sharmas.dhs.org> To: Patryk Zadarnowski <patrykz@ilion.eu.org> Cc: freebsd-hackers@FreeBSD.ORG Subject: Re: 64bit OS? Message-ID: <20000220004500.A25718@sharmas.dhs.org> In-Reply-To: <200002200528.QAA04257@mycenae.ilion.eu.org>; from Patryk Zadarnowski on Sun, Feb 20, 2000 at 04:28:51PM %2B1100 References: <20000219205850.A24847@sharmas.dhs.org> <200002200528.QAA04257@mycenae.ilion.eu.org>
next in thread | previous in thread | raw e-mail | index | archive | help
On Sun, Feb 20, 2000 at 04:28:51PM +1100, Patryk Zadarnowski wrote: > > On Sun, Feb 20, 2000 at 01:48:49PM +1100, Patryk Zadarnowski wrote: > > > > It looks like the hardware has to implement GPTs and know how to > > > > walk them. How can FreeBSD use them without hardware support ? > > > > > > No it doesn't. We've got software GPT implementations for both MIPS64 and > > > Alpha, and they're both peform very well in our somewhat hostile SASOS > > > conditions. I'm not sure why you think that a hardware walk is necessary: > > > > For performance reasons and memory efficiency reasons. My understanding of > > We must be careful here. Although you're getting a samll immediate performance > gain by not flushing the pipelines, the performance is killed if the working > set is larger than the TLB (as it usually is on a moderately-loaded system, > especially in presence of heavy IPC (eg. UNIX pipes)), in which case a smarter > data structure will usually increase the TLB coverage. The TLB (VHPT in the case of IA-64) can be made large to reduce the misses. Also, in the case of a VHPT miss, the software hander need not be any more expensive than it would have been in the absence of the VHPT. > > And don't forget that with VHPT you'll be getting nested TLB faults quite > frequently in a sparsely-populated page table (think shared libraries). > That's true only for the short format. Not for the long format. > which has an MMU vaguely resembling that of IA-64.). Besides, doesn't Linux > duplicate the structure anyway even when it uses a hardware-walked page table? No. L3 page tables are mapped into the linear page table. So the hardware walker just walks Linux L3 page tables. > before.) Besides, the amount of space saved due to a smarter page table data > structure more than compensates for the additional memory anyway. Agree. > > I think that's an important reason. A software only TLB miss handler > > would be inferior to a VHPT based solution on IA-64, IMO. > > It's the only justification Rumi Zahir (head of the IA-64 team) gave me when I > was complaining about it. (as in: ``why bother? 64 bit page tables are an > open problem and no other 64 bit platform I know of provides a hardware page > table walk''. BTW, does anoone know if HP-PA and IBM 64bit PPC implement a > hardware PT walk? I can't get the data on IBM's 64 bit Power3. But on 32 bit architectures, they use a hardware page walker. Researching more, I found someone who agrees with you about smart software page tables being better than hardware table walkers. http://hq.fsmlabs.com/~cort/papers/linuxppc-mm/html/ But I have a hard time beliving that processor architects at major companies are stupid in wasting transistors on hardware table walkers ;) -Arun To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?20000220004500.A25718>