Date: Thu, 7 Dec 2023 23:17:18 GMT From: John Baldwin <jhb@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 181afaaaee00 - main - vmm: implement VM_CAP_MASK_HWINTR on AMD CPUs Message-ID: <202312072317.3B7NHIwC026780@gitrepo.freebsd.org>
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The branch main has been updated by jhb: URL: https://cgit.FreeBSD.org/src/commit/?id=181afaaaee0025f948346fe8b9ec5356a0cdef97 commit 181afaaaee0025f948346fe8b9ec5356a0cdef97 Author: Bojan Novković <bojan.novkovic@fer.hr> AuthorDate: 2023-12-07 23:08:58 +0000 Commit: John Baldwin <jhb@FreeBSD.org> CommitDate: 2023-12-07 23:11:04 +0000 vmm: implement VM_CAP_MASK_HWINTR on AMD CPUs This patch implements the interrupt blocking VM capability on AMD CPUs. Implementing this capability allows the GDB stub to single-step a virtual machine without landing inside interrupt handlers. Reviewed by: jhb, corvink Sponsored by: Google, Inc. (GSoC 2022) Differential Revision: https://reviews.freebsd.org/D42299 --- sys/amd64/vmm/amd/svm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/sys/amd64/vmm/amd/svm.c b/sys/amd64/vmm/amd/svm.c index 1507377a0cfe..3fda9454090b 100644 --- a/sys/amd64/vmm/amd/svm.c +++ b/sys/amd64/vmm/amd/svm.c @@ -1725,6 +1725,10 @@ svm_inj_interrupts(struct svm_softc *sc, struct svm_vcpu *vcpu, int vector, need_intr_window; int extint_pending; + if (vcpu->caps & (1 << VM_CAP_MASK_HWINTR)) { + return; + } + state = svm_get_vmcb_state(vcpu); ctrl = svm_get_vmcb_ctrl(vcpu); @@ -2446,6 +2450,10 @@ svm_setcap(void *vcpui, int type, int val) vlapic = vm_lapic(vcpu->vcpu); vlapic->ipi_exit = val; break; + case VM_CAP_MASK_HWINTR: + vcpu->caps &= ~(1 << VM_CAP_MASK_HWINTR); + vcpu->caps |= (val << VM_CAP_MASK_HWINTR); + break; case VM_CAP_RFLAGS_TF: { uint64_t rflags; @@ -2529,6 +2537,9 @@ svm_getcap(void *vcpui, int type, int *retval) case VM_CAP_RFLAGS_TF: *retval = !!(vcpu->caps & (1 << VM_CAP_RFLAGS_TF)); break; + case VM_CAP_MASK_HWINTR: + *retval = !!(vcpu->caps & (1 << VM_CAP_MASK_HWINTR)); + break; default: error = ENOENT; break;
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