Date: Fri, 13 Dec 2013 22:12:37 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r259343 - stable/10/sys/arm/freescale/imx Message-ID: <201312132212.rBDMCbpC047319@svn.freebsd.org>
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Author: ian Date: Fri Dec 13 22:12:37 2013 New Revision: 259343 URL: http://svnweb.freebsd.org/changeset/base/259343 Log: MFC r257383, r257384: Add some bare-bones support for enabling usb and usbphy clocks. Add a "no-op" USB PHY driver for imx-family SoCs. Added: stable/10/sys/arm/freescale/imx/imx_nop_usbphy.c - copied unchanged from r257384, head/sys/arm/freescale/imx/imx_nop_usbphy.c Modified: stable/10/sys/arm/freescale/imx/files.imx51 stable/10/sys/arm/freescale/imx/files.imx53 stable/10/sys/arm/freescale/imx/imx51_ccm.c stable/10/sys/arm/freescale/imx/imx51_ccmreg.h stable/10/sys/arm/freescale/imx/imx_machdep.h Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/freescale/imx/files.imx51 ============================================================================== --- stable/10/sys/arm/freescale/imx/files.imx51 Fri Dec 13 22:08:31 2013 (r259342) +++ stable/10/sys/arm/freescale/imx/files.imx51 Fri Dec 13 22:12:37 2013 (r259343) @@ -37,7 +37,8 @@ dev/ata/chipsets/ata-fsl.c optional imx # UART driver dev/uart/uart_dev_imx.c optional uart -# USB join controller (1 OTG, 3 EHCI) +# USB OH3 controller (1 OTG, 3 EHCI) +arm/freescale/imx/imx_nop_usbphy.c optional echi dev/usb/controller/ehci_imx.c optional ehci # Watchdog Modified: stable/10/sys/arm/freescale/imx/files.imx53 ============================================================================== --- stable/10/sys/arm/freescale/imx/files.imx53 Fri Dec 13 22:08:31 2013 (r259342) +++ stable/10/sys/arm/freescale/imx/files.imx53 Fri Dec 13 22:12:37 2013 (r259343) @@ -37,7 +37,8 @@ arm/freescale/imx/imx51_ccm.c standard # i.MX5xx PATA controller dev/ata/chipsets/ata-fsl.c optional imxata -# USB join controller (1 OTG, 3 EHCI) +# USB OH3 controller (1 OTG, 3 EHCI) +arm/freescale/imx/imx_nop_usbphy.c optional ehci dev/usb/controller/ehci_imx.c optional ehci # Watchdog Modified: stable/10/sys/arm/freescale/imx/imx51_ccm.c ============================================================================== --- stable/10/sys/arm/freescale/imx/imx51_ccm.c Fri Dec 13 22:08:31 2013 (r259342) +++ stable/10/sys/arm/freescale/imx/imx51_ccm.c Fri Dec 13 22:12:37 2013 (r259343) @@ -83,6 +83,7 @@ __FBSDID("$FreeBSD$"); #include <arm/freescale/imx/imx51_ccmvar.h> #include <arm/freescale/imx/imx51_ccmreg.h> #include <arm/freescale/imx/imx51_dpllreg.h> +#include <arm/freescale/imx/imx_machdep.h> #define IMXCCMDEBUG #undef IMXCCMDEBUG @@ -473,3 +474,78 @@ imx51_get_clk_gating(int clk_src) return ((reg >> (clk_src % CCMR_CCGR_NSOURCE) * 2) & 0x03); } +/* + * Code from here down is temporary, in lieu of a SoC-independent clock API. + */ + +void +imx_ccm_usb_enable(device_t dev) +{ + uint32_t regval; + + /* + * Select PLL2 as the source for the USB clock. + * The default is PLL3, but U-boot changes it to PLL2. + */ + regval = bus_read_4(ccm_softc->res[0], CCMC_CSCMR1); + regval &= ~CSCMR1_USBOH3_CLK_SEL_MASK; + regval |= 1 << CSCMR1_USBOH3_CLK_SEL_SHIFT; + bus_write_4(ccm_softc->res[0], CCMC_CSCMR1, regval); + + /* + * Set the USB clock pre-divider to div-by-5, post-divider to div-by-2. + */ + regval = bus_read_4(ccm_softc->res[0], CCMC_CSCDR1); + regval &= ~CSCDR1_USBOH3_CLK_PODF_MASK; + regval &= ~CSCDR1_USBOH3_CLK_PRED_MASK; + regval |= 4 << CSCDR1_USBOH3_CLK_PRED_SHIFT; + regval |= 1 << CSCDR1_USBOH3_CLK_PODF_SHIFT; + bus_write_4(ccm_softc->res[0], CCMC_CSCDR1, regval); + + /* + * The same two clocks gates are used on imx51 and imx53. + */ + imx51_clk_gating(CCGR_USBOH3_IPG_AHB_CLK, CCGR_CLK_MODE_ALWAYS); + imx51_clk_gating(CCGR_USBOH3_60M_CLK, CCGR_CLK_MODE_ALWAYS); +} + +void +imx_ccm_usbphy_enable(device_t dev) +{ + uint32_t regval; + + /* + * Select PLL3 as the source for the USBPHY clock. U-boot does this + * only for imx53, but the bit exists on imx51. That seems a bit + * strange, but we'll go with it until more is known. + */ + if (imx_soc_type() == IMXSOC_53) { + regval = bus_read_4(ccm_softc->res[0], CCMC_CSCMR1); + regval |= 1 << CSCMR1_USBPHY_CLK_SEL_SHIFT; + bus_write_4(ccm_softc->res[0], CCMC_CSCMR1, regval); + } + + /* + * For the imx51 there's just one phy gate control, enable it. + */ + if (imx_soc_type() == IMXSOC_51) { + imx51_clk_gating(CCGR_USB_PHY_CLK, CCGR_CLK_MODE_ALWAYS); + return; + } + + /* + * For imx53 we don't have a full set of clock defines yet, but the + * datasheet says: + * gate reg 4, bits 13-12 usb ph2 clock (usb_phy2_clk_enable) + * gate reg 4, bits 11-10 usb ph1 clock (usb_phy1_clk_enable) + * + * We should use the fdt data for the device to figure out which of + * the two we're working on, but for now just turn them both on. + */ + if (imx_soc_type() == IMXSOC_53) { + imx51_clk_gating(__CCGR_NUM(4, 5), CCGR_CLK_MODE_ALWAYS); + imx51_clk_gating(__CCGR_NUM(4, 6), CCGR_CLK_MODE_ALWAYS); + return; + } +} + Modified: stable/10/sys/arm/freescale/imx/imx51_ccmreg.h ============================================================================== --- stable/10/sys/arm/freescale/imx/imx51_ccmreg.h Fri Dec 13 22:08:31 2013 (r259342) +++ stable/10/sys/arm/freescale/imx/imx51_ccmreg.h Fri Dec 13 22:12:37 2013 (r259343) @@ -114,12 +114,20 @@ #define CCMC_CSCMR1 0x001c #define CSCMR1_UART_CLK_SEL_SHIFT 24 #define CSCMR1_UART_CLK_SEL_MASK 0x03000000 +#define CSCMR1_USBPHY_CLK_SEL_SHIFT 26 +#define CSCMR1_USBPHY_CLK_SEL_MASK 0x04000000 +#define CSCMR1_USBOH3_CLK_SEL_SHIFT 22 +#define CSCMR1_USBOH3_CLK_SEL_MASK 0x00c00000 #define CCMC_CSCMR2 0x0020 #define CCMC_CSCDR1 0x0024 #define CSCDR1_UART_CLK_PRED_SHIFT 3 #define CSCDR1_UART_CLK_PRED_MASK 0x00000038 #define CSCDR1_UART_CLK_PODF_SHIFT 0 #define CSCDR1_UART_CLK_PODF_MASK 0x00000007 +#define CSCDR1_USBOH3_CLK_PRED_SHIFT 8 +#define CSCDR1_USBOH3_CLK_PRED_MASK 0x00000700 +#define CSCDR1_USBOH3_CLK_PODF_SHIFT 6 +#define CSCDR1_USBOH3_CLK_PODF_MASK 0x000000c0 #define CCMC_CS1CDR 0x0028 #define CCMC_CS2CDR 0x002c #define CCMC_CDCDR 0x0030 Modified: stable/10/sys/arm/freescale/imx/imx_machdep.h ============================================================================== --- stable/10/sys/arm/freescale/imx/imx_machdep.h Fri Dec 13 22:08:31 2013 (r259342) +++ stable/10/sys/arm/freescale/imx/imx_machdep.h Fri Dec 13 22:12:37 2013 (r259343) @@ -56,5 +56,21 @@ u_int imx_soc_family(void); void imx_devmap_init(void); +/* + * We need a clock management system that works across unrelated SoCs and + * devices. For now, to keep imx development moving, define some barebones + * functionality that can be shared within the imx family by having each SoC + * implement functions with a common name. + * + * The usb enable functions are best-effort. They turn on the usb otg, host, + * and phy clocks in a SoC-specific manner, but it may take a lot more than that + * to make usb work on a given board. In particular, it can require specific + * pinmux setup of gpio pins connected to external phy parts, voltage regulators + * and overcurrent detectors, and so on. On such boards, u-boot or other early + * board setup code has to handle those things. + */ +void imx_ccm_usb_enable(device_t _usbdev); +void imx_ccm_usbphy_enable(device_t _phydev); + #endif Copied: stable/10/sys/arm/freescale/imx/imx_nop_usbphy.c (from r257384, head/sys/arm/freescale/imx/imx_nop_usbphy.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ stable/10/sys/arm/freescale/imx/imx_nop_usbphy.c Fri Dec 13 22:12:37 2013 (r259343, copy of r257384, head/sys/arm/freescale/imx/imx_nop_usbphy.c) @@ -0,0 +1,118 @@ +/*- + * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * USBPHY "no-op" driver for Freescale family of SoCs. This driver is used on + * SoCs which have usbphy hardware whose clocks need to be enabled, but no other + * action has to be taken to make the hardware work. + */ + +#include "opt_bus.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/bus.h> +#include <sys/rman.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <machine/bus.h> + +#include <arm/freescale/imx/imx_machdep.h> + +/* + * Table of supported FDT compat strings. + */ +static struct ofw_compat_data compat_data[] = { + {"nop-usbphy", true}, + {"usb-nop-xceiv", true}, + {NULL, false}, +}; + +struct usbphy_softc { + device_t dev; + u_int phy_num; +}; + +static int +usbphy_detach(device_t dev) +{ + + return (0); +} + +static int +usbphy_attach(device_t dev) +{ + struct usbphy_softc *sc; + + sc = device_get_softc(dev); + + /* + * Turn on the phy clocks. + */ + imx_ccm_usbphy_enable(dev); + + return (0); +} + +static int +usbphy_probe(device_t dev) +{ + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { + device_set_desc(dev, "Freescale USB PHY"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static device_method_t usbphy_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, usbphy_probe), + DEVMETHOD(device_attach, usbphy_attach), + DEVMETHOD(device_detach, usbphy_detach), + + DEVMETHOD_END +}; + +static driver_t usbphy_driver = { + "usbphy", + usbphy_methods, + sizeof(struct usbphy_softc) +}; + +static devclass_t usbphy_devclass; + +DRIVER_MODULE(usbphy, simplebus, usbphy_driver, usbphy_devclass, 0, 0); +
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