Date: Thu, 17 Jun 2004 15:32:03 -0400 From: Don Bowman <don@sandvine.com> To: "'current@freebsd.org'" <current@freebsd.org> Subject: STI, HLT in acpi_cpu_idle_c1 Message-ID: <FE045D4D9F7AED4CBFF1B3B813C85337051D900F@mail.sandvine.com>
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in the intel instruction manual, the effect of STI is that interrupts are enabled *after* the next instruction. ie: sti ret ... the return is still run with interrupts disabled (if they were prior to the STI). In acpi_cpu_idle_c1, it does: sti hlt shouldn't there be a NOP in there so that interrupts are guaranteed on? We have traced down a lockup of the system with a TAP emulator, and found that three processors are in acpi_cpu_idle with bit 9 of EFLAGS clear, indicating interrupts are disabled. The fourth processor is spinning with nothing to do (since hardclock etc don't come to it). Suggestions? Am i off base on the sti/hlt? Is there another problem that i might be running into? --don
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