Date: Sat, 29 Oct 2016 01:24:30 +0000 (UTC) From: Justin Hibbits <jhibbits@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r308073 - in head/sys/powerpc: include powerpc Message-ID: <201610290124.u9T1OU0G028826@repo.freebsd.org>
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Author: jhibbits Date: Sat Oct 29 01:24:30 2016 New Revision: 308073 URL: https://svnweb.freebsd.org/changeset/base/308073 Log: Add the SPE feature mask for e500v1 and e500v2 On e500v2 SoCs it will now print: cpu0: Features 84e08000<PPC32,MMU,SPE,EFPS,EFPD,BOOKE> at bootup. Modified: head/sys/powerpc/include/cpu.h head/sys/powerpc/powerpc/cpu.c Modified: head/sys/powerpc/include/cpu.h ============================================================================== --- head/sys/powerpc/include/cpu.h Sat Oct 29 01:22:55 2016 (r308072) +++ head/sys/powerpc/include/cpu.h Sat Oct 29 01:24:30 2016 (r308073) @@ -56,6 +56,9 @@ extern int cpu_features2; #define PPC_FEATURE_HAS_FPU 0x08000000 #define PPC_FEATURE_HAS_MMU 0x04000000 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000 +#define PPC_FEATURE_HAS_SPE 0x00800000 +#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 +#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 #define PPC_FEATURE_BOOKE 0x00008000 #define PPC_FEATURE_SMT 0x00004000 #define PPC_FEATURE_ARCH_2_05 0x00001000 @@ -70,7 +73,8 @@ extern int cpu_features2; #define PPC_FEATURE_BITMASK \ "\20" \ "\040PPC32\037PPC64\035ALTIVEC\034FPU\033MMU\031UNIFIEDCACHE" \ - "\020BOOKE\017SMT\015ARCH205\013DFP\011ARCH206\010VSX" + "\030SPE\027SPESFP\026DPESFP\020BOOKE\017SMT\015ARCH205\013DFP" \ + "\011ARCH206\010VSX" #define PPC_FEATURE2_BITMASK \ "\20" \ "\040ARCH207\037HTM\032VCRYPTO" Modified: head/sys/powerpc/powerpc/cpu.c ============================================================================== --- head/sys/powerpc/powerpc/cpu.c Sat Oct 29 01:22:55 2016 (r308072) +++ head/sys/powerpc/powerpc/cpu.c Sat Oct 29 01:24:30 2016 (r308073) @@ -180,9 +180,12 @@ static const struct cputab models[] = { { "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN, PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, { "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN, - PPC_FEATURE_BOOKE, 0, cpu_booke_setup }, + PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE | PPC_FEATURE_HAS_EFP_SINGLE, + 0, cpu_booke_setup }, { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN, - PPC_FEATURE_BOOKE, 0, cpu_booke_setup }, + PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE | + PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE, 0, + cpu_booke_setup }, { "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN, PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_FPU, 0, cpu_booke_setup }, { "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN,
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