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Date:      Fri, 14 Sep 2012 09:38:54 +0000 (UTC)
From:      Grzegorz Bernacki <gber@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r240486 - in head/sys/arm: arm include
Message-ID:  <201209140938.q8E9csJB089497@svn.freebsd.org>
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Author: gber
Date: Fri Sep 14 09:38:54 2012
New Revision: 240486
URL: http://svn.freebsd.org/changeset/base/240486

Log:
  Support identification of new PJ4B cores.
  
  Obtained from:	Semihalf

Modified:
  head/sys/arm/arm/cpufunc.c
  head/sys/arm/arm/identcpu.c
  head/sys/arm/include/armreg.h

Modified: head/sys/arm/arm/cpufunc.c
==============================================================================
--- head/sys/arm/arm/cpufunc.c	Fri Sep 14 09:36:35 2012	(r240485)
+++ head/sys/arm/arm/cpufunc.c	Fri Sep 14 09:38:54 2012	(r240486)
@@ -1415,6 +1415,7 @@ set_cpufuncs()
 #if defined(CPU_MV_PJ4B)
 	if (cputype == CPU_ID_MV88SV581X_V6 ||
 	    cputype == CPU_ID_MV88SV581X_V7 ||
+	    cputype == CPU_ID_MV88SV584X_V7 ||
 	    cputype == CPU_ID_ARM_88SV581X_V6 ||
 	    cputype == CPU_ID_ARM_88SV581X_V7) {
 		if (cpu_pfr(0) & ARM_PFR0_THUMBEE_MASK)
@@ -1425,8 +1426,8 @@ set_cpufuncs()
 		get_cachetype_cp15();
 		pmap_pte_init_mmu_v6();
 		goto out;
-	} else if (cputype == CPU_ID_ARM_88SV584X ||
-	    cputype == CPU_ID_MV88SV584X) {
+	} else if (cputype == CPU_ID_ARM_88SV584X_V6 ||
+	    cputype == CPU_ID_MV88SV584X_V6) {
 		cpufuncs = pj4bv6_cpufuncs;
 		get_cachetype_cp15();
 		pmap_pte_init_mmu_v6();

Modified: head/sys/arm/arm/identcpu.c
==============================================================================
--- head/sys/arm/arm/identcpu.c	Fri Sep 14 09:36:35 2012	(r240485)
+++ head/sys/arm/arm/identcpu.c	Fri Sep 14 09:38:54 2012	(r240486)
@@ -321,9 +321,11 @@ const struct cpuidtab cpuids[] = {
 	  generic_steppings },
 	{ CPU_ID_ARM_88SV581X_V7, CPU_CLASS_MARVELL,	"Sheeva 88SV581x",
 	  generic_steppings },
-	{ CPU_ID_MV88SV584X,	CPU_CLASS_MARVELL,	"Sheeva 88SV584x",
+	{ CPU_ID_MV88SV584X_V6,	CPU_CLASS_MARVELL,	"Sheeva 88SV584x",
 	  generic_steppings },
-	{ CPU_ID_ARM_88SV584X,	CPU_CLASS_MARVELL,	"Sheeva 88SV584x",
+	{ CPU_ID_ARM_88SV584X_V6, CPU_CLASS_MARVELL,	"Sheeva 88SV584x",
+	  generic_steppings },
+	{ CPU_ID_MV88SV584X_V7,	CPU_CLASS_MARVELL,	"Sheeva 88SV584x",
 	  generic_steppings },
 
 	{ 0, CPU_CLASS_NONE, NULL, NULL }

Modified: head/sys/arm/include/armreg.h
==============================================================================
--- head/sys/arm/include/armreg.h	Fri Sep 14 09:36:35 2012	(r240485)
+++ head/sys/arm/include/armreg.h	Fri Sep 14 09:38:54 2012	(r240486)
@@ -170,11 +170,12 @@
 
 #define CPU_ID_MV88SV581X_V6		0x560F5810 /* Marvell Sheeva 88SV581x v6 Core */
 #define CPU_ID_MV88SV581X_V7		0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */
-#define CPU_ID_MV88SV584X		0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */
+#define CPU_ID_MV88SV584X_V6		0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */
+#define CPU_ID_MV88SV584X_V7		0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */
 /* Marvell's CPUIDs with ARM ID in implementor field */
 #define CPU_ID_ARM_88SV581X_V6		0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */
 #define CPU_ID_ARM_88SV581X_V7		0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */
-#define CPU_ID_ARM_88SV584X		0x410FB024 /* Marvell Sheeva 88SV584x v6 Core */
+#define CPU_ID_ARM_88SV584X_V6		0x410FB020 /* Marvell Sheeva 88SV584x v6 Core */
 
 #define	CPU_ID_FA526		0x66015260
 #define	CPU_ID_FA626TE		0x66056260

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