Date: Mon, 23 Mar 2009 14:36:50 +0000 (UTC) From: Marius Strobl <marius@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r190319 - head/sys/dev/bge Message-ID: <200903231436.n2NEao58012045@svn.freebsd.org>
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Author: marius Date: Mon Mar 23 14:36:50 2009 New Revision: 190319 URL: http://svn.freebsd.org/changeset/base/190319 Log: - Ensure that INTx isn't disabled, as these chips apparently have a quirk requiring it to be enabled even when using MSI. This makes the latter work again after r189285. - Remove a comment which no longer applies since r190194. Modified: head/sys/dev/bge/if_bge.c head/sys/dev/bge/if_bgereg.h Modified: head/sys/dev/bge/if_bge.c ============================================================================== --- head/sys/dev/bge/if_bge.c Mon Mar 23 12:07:29 2009 (r190318) +++ head/sys/dev/bge/if_bge.c Mon Mar 23 14:36:50 2009 (r190319) @@ -1295,8 +1295,7 @@ bge_stop_fw(sc) } /* - * Do endian, PCI and DMA initialization. Also check the on-board ROM - * self-test results. + * Do endian, PCI and DMA initialization. */ static int bge_chipinit(struct bge_softc *sc) @@ -1404,9 +1403,11 @@ bge_chipinit(struct bge_softc *sc) /* * Disable memory write invalidate. Apparently it is not supported - * properly by these devices. + * properly by these devices. Also ensure that INTx isn't disabled, + * as these chips need it even when using MSI. */ - PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); + PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, + PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); /* Set the timer prescaler (always 66Mhz) */ CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); Modified: head/sys/dev/bge/if_bgereg.h ============================================================================== --- head/sys/dev/bge/if_bgereg.h Mon Mar 23 12:07:29 2009 (r190318) +++ head/sys/dev/bge/if_bgereg.h Mon Mar 23 14:36:50 2009 (r190319) @@ -404,6 +404,9 @@ #ifndef PCIM_CMD_MWIEN #define PCIM_CMD_MWIEN 0x0010 #endif +#ifndef PCIM_CMD_INTxDIS +#define PCIM_CMD_INTxDIS 0x0400 +#endif /* * High priority mailbox registers
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