Date: Fri, 12 Jan 2018 06:37:53 +0000 (UTC) From: Eitan Adler <eadler@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r327865 - head/sys/dev/e1000 Message-ID: <201801120637.w0C6brSX069884@repo.freebsd.org>
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Author: eadler Date: Fri Jan 12 06:37:53 2018 New Revision: 327865 URL: https://svnweb.freebsd.org/changeset/base/327865 Log: sys/dev/e1000: fix uses of 1 << 31 Reviewed by: erj (D13858) Modified: head/sys/dev/e1000/e1000_82575.h head/sys/dev/e1000/e1000_ich8lan.c head/sys/dev/e1000/e1000_regs.h Modified: head/sys/dev/e1000/e1000_82575.h ============================================================================== --- head/sys/dev/e1000/e1000_82575.h Fri Jan 12 06:36:44 2018 (r327864) +++ head/sys/dev/e1000/e1000_82575.h Fri Jan 12 06:37:53 2018 (r327865) @@ -385,7 +385,7 @@ struct e1000_adv_tx_context_desc { #define E1000_ETQF_FILTER_ENABLE (1 << 26) #define E1000_ETQF_IMM_INT (1 << 29) #define E1000_ETQF_1588 (1 << 30) -#define E1000_ETQF_QUEUE_ENABLE (1 << 31) +#define E1000_ETQF_QUEUE_ENABLE (1U << 31) /* * ETQF filter list: one static filter per filter consumer. This is * to avoid filter collisions later. Add new filters @@ -412,7 +412,7 @@ struct e1000_adv_tx_context_desc { #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 #define E1000_DTXSWC_LLE_SHIFT 16 -#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ +#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1U << 31) /* global VF LB enable */ /* Easy defines for setting default pool, would normally be left a zero */ #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 Modified: head/sys/dev/e1000/e1000_ich8lan.c ============================================================================== --- head/sys/dev/e1000/e1000_ich8lan.c Fri Jan 12 06:36:44 2018 (r327864) +++ head/sys/dev/e1000/e1000_ich8lan.c Fri Jan 12 06:37:53 2018 (r327865) @@ -5202,7 +5202,7 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1 /* Device Status */ if (hw->mac.type == e1000_ich8lan) { reg = E1000_READ_REG(hw, E1000_STATUS); - reg &= ~(1 << 31); + reg &= ~(1U << 31); E1000_WRITE_REG(hw, E1000_STATUS, reg); } Modified: head/sys/dev/e1000/e1000_regs.h ============================================================================== --- head/sys/dev/e1000/e1000_regs.h Fri Jan 12 06:36:44 2018 (r327864) +++ head/sys/dev/e1000/e1000_regs.h Fri Jan 12 06:37:53 2018 (r327865) @@ -215,7 +215,7 @@ /* QAV Tx mode control register bitfields masks */ #define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */ #define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */ -#define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */ +#define E1000_TQAVCC_QUEUE_MODE (1U << 31) /* SP vs. SR Tx mode */ /* Good transmitted packets counter registers */ #define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n)))
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