Date: Wed, 7 Mar 2018 09:58:36 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r330574 - head/sys/arm64/arm64 Message-ID: <201803070958.w279waNW008233@repo.freebsd.org>
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Author: andrew Date: Wed Mar 7 09:58:36 2018 New Revision: 330574 URL: https://svnweb.freebsd.org/changeset/base/330574 Log: Restrict the arm64 DMAP region to the 1G blocks where we have at least one physical page. This is in preparation for limiting it further as this is needed on some hardware, however testing has shown issues with further restricting the DMAP and ACPI. Sponsored by: DARPA, AFRL Sponsored by: Cavium (Hardware) Modified: head/sys/arm64/arm64/pmap.c Modified: head/sys/arm64/arm64/pmap.c ============================================================================== --- head/sys/arm64/arm64/pmap.c Wed Mar 7 09:40:41 2018 (r330573) +++ head/sys/arm64/arm64/pmap.c Wed Mar 7 09:58:36 2018 (r330574) @@ -570,21 +570,32 @@ pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t mi vm_offset_t va; vm_paddr_t pa; u_int l1_slot; + int i; - pa = dmap_phys_base = min_pa & ~L1_OFFSET; - va = DMAP_MIN_ADDRESS; - for (; va < DMAP_MAX_ADDRESS && pa < max_pa; - pa += L1_SIZE, va += L1_SIZE, l1_slot++) { - l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT); + dmap_phys_base = min_pa & ~L1_OFFSET; + dmap_phys_max = 0; + dmap_max_addr = 0; - pmap_load_store(&pagetable_dmap[l1_slot], - (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN | - ATTR_IDX(CACHED_MEMORY) | L1_BLOCK); - } + for (i = 0; i < (physmap_idx * 2); i += 2) { + pa = physmap[i] & ~L1_OFFSET; + va = pa - dmap_phys_base + DMAP_MIN_ADDRESS; - /* Set the upper limit of the DMAP region */ - dmap_phys_max = pa; - dmap_max_addr = va; + for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1]; + pa += L1_SIZE, va += L1_SIZE) { + l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT); + /* We already have an entry */ + if (pagetable_dmap[l1_slot] != 0) + continue; + pmap_load_store(&pagetable_dmap[l1_slot], + (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN | + ATTR_IDX(CACHED_MEMORY) | L1_BLOCK); + } + + if (pa > dmap_phys_max) { + dmap_phys_max = pa; + dmap_max_addr = va; + } + } cpu_tlb_flushID(); }
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