Date: Fri, 14 Dec 2018 07:57:01 +0000 (UTC) From: Kashyap D Desai <kadesai@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r342059 - head/sys/dev/mrsas Message-ID: <201812140757.wBE7v1o8082618@repo.freebsd.org>
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Author: kadesai Date: Fri Dec 14 07:57:00 2018 New Revision: 342059 URL: https://svnweb.freebsd.org/changeset/base/342059 Log: This patch will add support for next generation(SAS3.5) of Tri mode(SAS, SATA, NVMe) MegaRAID adapters. Submitted by: Sumit Saxena <sumit.saxena@broadcom.com> Reviewed by: Kashyap Desai <Kashyap.Desai@broadcom.com> Approved by: ken MFC after: 3 days Sponsored by: Broadcom Inc Modified: head/sys/dev/mrsas/mrsas.c head/sys/dev/mrsas/mrsas.h head/sys/dev/mrsas/mrsas_cam.c head/sys/dev/mrsas/mrsas_fp.c Modified: head/sys/dev/mrsas/mrsas.c ============================================================================== --- head/sys/dev/mrsas/mrsas.c Fri Dec 14 03:55:08 2018 (r342058) +++ head/sys/dev/mrsas/mrsas.c Fri Dec 14 07:57:00 2018 (r342059) @@ -190,6 +190,12 @@ MRSAS_CTLR_ID device_table[] = { {0x1000, MRSAS_INTRUDER_24, 0xffff, 0xffff, "AVAGO Intruder_24 SAS Controller"}, {0x1000, MRSAS_CUTLASS_52, 0xffff, 0xffff, "AVAGO Cutlass_52 SAS Controller"}, {0x1000, MRSAS_CUTLASS_53, 0xffff, 0xffff, "AVAGO Cutlass_53 SAS Controller"}, + {0x1000, MRSAS_VENTURA, 0xffff, 0xffff, "AVAGO Ventura SAS Controller"}, + {0x1000, MRSAS_CRUSADER, 0xffff, 0xffff, "AVAGO Crusader SAS Controller"}, + {0x1000, MRSAS_HARPOON, 0xffff, 0xffff, "AVAGO Harpoon SAS Controller"}, + {0x1000, MRSAS_TOMCAT, 0xffff, 0xffff, "AVAGO Tomcat SAS Controller"}, + {0x1000, MRSAS_VENTURA_4PORT, 0xffff, 0xffff, "AVAGO Ventura_4Port SAS Controller"}, + {0x1000, MRSAS_CRUSADER_4PORT, 0xffff, 0xffff, "AVAGO Crusader_4Port SAS Controller"}, {0, 0, 0, 0, NULL} }; @@ -815,7 +821,7 @@ static int mrsas_attach(device_t dev) { struct mrsas_softc *sc = device_get_softc(dev); - uint32_t cmd, bar, error; + uint32_t cmd, error; memset(sc, 0, sizeof(struct mrsas_softc)); @@ -830,7 +836,14 @@ mrsas_attach(device_t dev) (sc->device_id == MRSAS_CUTLASS_52) || (sc->device_id == MRSAS_CUTLASS_53)) { sc->mrsas_gen3_ctrl = 1; - } + } else if ((sc->device_id == MRSAS_VENTURA) || + (sc->device_id == MRSAS_CRUSADER) || + (sc->device_id == MRSAS_HARPOON) || + (sc->device_id == MRSAS_TOMCAT) || + (sc->device_id == MRSAS_VENTURA_4PORT) || + (sc->device_id == MRSAS_CRUSADER_4PORT)) { + sc->is_ventura = true; + } mrsas_get_tunables(sc); @@ -845,9 +858,12 @@ mrsas_attach(device_t dev) cmd |= PCIM_CMD_BUSMASTEREN; pci_write_config(dev, PCIR_COMMAND, cmd, 2); - bar = pci_read_config(dev, MRSAS_PCI_BAR1, 4); + /* For Ventura system registers are mapped to BAR0 */ + if (sc->is_ventura) + sc->reg_res_id = PCIR_BAR(0); /* BAR0 offset */ + else + sc->reg_res_id = PCIR_BAR(1); /* BAR1 offset */ - sc->reg_res_id = MRSAS_PCI_BAR1;/* BAR1 offset */ if ((sc->reg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &(sc->reg_res_id), RF_ACTIVE)) == NULL) { @@ -1648,7 +1664,7 @@ mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t M */ if (threshold_reply_count >= THRESHOLD_REPLY_COUNT) { if (sc->msix_enable) { - if (sc->mrsas_gen3_ctrl) + if (sc->msix_combined) mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8], ((MSIxIndex & 0x7) << 24) | sc->last_reply_idx[MSIxIndex]); @@ -1669,7 +1685,7 @@ mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t M /* Clear response interrupt */ if (sc->msix_enable) { - if (sc->mrsas_gen3_ctrl) { + if (sc->msix_combined) { mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8], ((MSIxIndex & 0x7) << 24) | sc->last_reply_idx[MSIxIndex]); @@ -2177,6 +2193,15 @@ mrsas_init_fw(struct mrsas_softc *sc) >> MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT) + 1; fw_msix_count = sc->msix_vectors; + if ((sc->mrsas_gen3_ctrl && (sc->msix_vectors > 8)) || + (sc->is_ventura && (sc->msix_vectors > 16))) + sc->msix_combined = true; + /* + * Save 1-15 reply post index + * address to local memory Index 0 + * is already saved from reg offset + * MPI2_REPLY_POST_HOST_INDEX_OFFSET + */ for (loop = 1; loop < MR_MAX_MSIX_REG_ARRAY; loop++) { sc->msix_reg_offset[loop] = @@ -2199,6 +2224,14 @@ mrsas_init_fw(struct mrsas_softc *sc) "Online CPU %d Current MSIX <%d>\n", fw_msix_count, mp_ncpus, sc->msix_vectors); } + /* + * MSI-X host index 0 is common for all adapter. + * It is used for all MPT based Adapters. + */ + if (sc->msix_combined) { + sc->msix_reg_offset[0] = + MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET; + } if (mrsas_init_adapter(sc) != SUCCESS) { device_printf(sc->mrsas_dev, "Adapter initialize Fail.\n"); return (1); @@ -2476,7 +2509,7 @@ mrsas_ioc_init(struct mrsas_softc *sc) init_frame->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; /* driver support Extended MSIX */ - if (sc->mrsas_gen3_ctrl) { + if (sc->mrsas_gen3_ctrl || sc->is_ventura) { init_frame->driver_operations. mfi_capabilities.support_additional_msix = 1; } @@ -3591,7 +3624,7 @@ mrsas_build_mptmfi_passthru(struct mrsas_softc *sc, st io_req = mpt_cmd->io_request; - if (sc->mrsas_gen3_ctrl) { + if (sc->mrsas_gen3_ctrl || sc->is_ventura) { pMpi25IeeeSgeChain64_t sgl_ptr_end = (pMpi25IeeeSgeChain64_t)&io_req->SGL; sgl_ptr_end += sc->max_sge_in_main_msg - 1; Modified: head/sys/dev/mrsas/mrsas.h ============================================================================== --- head/sys/dev/mrsas/mrsas.h Fri Dec 14 03:55:08 2018 (r342058) +++ head/sys/dev/mrsas/mrsas.h Fri Dec 14 07:57:00 2018 (r342059) @@ -84,9 +84,13 @@ __FBSDID("$FreeBSD$"); #define MRSAS_INTRUDER_24 0x00cf #define MRSAS_CUTLASS_52 0x0052 #define MRSAS_CUTLASS_53 0x0053 -#define MRSAS_PCI_BAR0 0x10 -#define MRSAS_PCI_BAR1 0x14 -#define MRSAS_PCI_BAR2 0x1C +/* Gen3.5 Conroller */ +#define MRSAS_VENTURA 0x0014 +#define MRSAS_CRUSADER 0x0015 +#define MRSAS_HARPOON 0x0016 +#define MRSAS_TOMCAT 0x0017 +#define MRSAS_VENTURA_4PORT 0x001B +#define MRSAS_CRUSADER_4PORT 0x001C /* * Firmware State Defines @@ -2912,6 +2916,9 @@ struct mrsas_softc { u_int32_t old_map_sz; u_int32_t new_map_sz; u_int32_t drv_map_sz; + + boolean_t is_ventura; + boolean_t msix_combined; /* Non dma-able memory. Driver local copy. */ MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; Modified: head/sys/dev/mrsas/mrsas_cam.c ============================================================================== --- head/sys/dev/mrsas/mrsas_cam.c Fri Dec 14 03:55:08 2018 (r342058) +++ head/sys/dev/mrsas/mrsas_cam.c Fri Dec 14 07:57:00 2018 (r342059) @@ -1103,7 +1103,8 @@ mrsas_build_syspdio(struct mrsas_softc *sc, struct mrs * Because the NON RW cmds will now go via FW Queue * and not the Exception queue */ - io_request->IoFlags |= MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH; + if (sc->mrsas_gen3_ctrl || sc->is_ventura) + io_request->IoFlags |= MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH; cmd->request_desc->SCSIIO.RequestFlags = (MPI2_REQ_DESCRIPT_FLAGS_FP_IO << @@ -1233,7 +1234,7 @@ mrsas_data_load_cb(void *arg, bus_dma_segment_t *segs, io_request = cmd->io_request; sgl_ptr = (pMpi25IeeeSgeChain64_t)&io_request->SGL; - if (sc->mrsas_gen3_ctrl) { + if (sc->mrsas_gen3_ctrl || sc->is_ventura) { pMpi25IeeeSgeChain64_t sgl_ptr_end = sgl_ptr; sgl_ptr_end += sc->max_sge_in_main_msg - 1; @@ -1244,7 +1245,7 @@ mrsas_data_load_cb(void *arg, bus_dma_segment_t *segs, sgl_ptr->Address = segs[i].ds_addr; sgl_ptr->Length = segs[i].ds_len; sgl_ptr->Flags = 0; - if (sc->mrsas_gen3_ctrl) { + if (sc->mrsas_gen3_ctrl || sc->is_ventura) { if (i == nseg - 1) sgl_ptr->Flags = IEEE_SGE_FLAGS_END_OF_LIST; } @@ -1254,7 +1255,7 @@ mrsas_data_load_cb(void *arg, bus_dma_segment_t *segs, (nseg > sc->max_sge_in_main_msg)) { pMpi25IeeeSgeChain64_t sg_chain; - if (sc->mrsas_gen3_ctrl) { + if (sc->mrsas_gen3_ctrl || sc->is_ventura) { if ((cmd->io_request->IoFlags & MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) != MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) cmd->io_request->ChainOffset = sc->chain_offset_io_request; @@ -1263,7 +1264,7 @@ mrsas_data_load_cb(void *arg, bus_dma_segment_t *segs, } else cmd->io_request->ChainOffset = sc->chain_offset_io_request; sg_chain = sgl_ptr; - if (sc->mrsas_gen3_ctrl) + if (sc->mrsas_gen3_ctrl || sc->is_ventura) sg_chain->Flags = IEEE_SGE_FLAGS_CHAIN_ELEMENT; else sg_chain->Flags = (IEEE_SGE_FLAGS_CHAIN_ELEMENT | MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR); Modified: head/sys/dev/mrsas/mrsas_fp.c ============================================================================== --- head/sys/dev/mrsas/mrsas_fp.c Fri Dec 14 03:55:08 2018 (r342058) +++ head/sys/dev/mrsas/mrsas_fp.c Fri Dec 14 07:57:00 2018 (r342059) @@ -773,8 +773,9 @@ mr_spanset_get_phy_params(struct mrsas_softc *sc, u_in *pDevHandle = MR_PdDevHandleGet(pd, map); else { *pDevHandle = MR_PD_INVALID; - if ((raid->level >= 5) && ((!sc->mrsas_gen3_ctrl) || (sc->mrsas_gen3_ctrl && - raid->regTypeReqOnRead != REGION_TYPE_UNUSED))) + if ((raid->level >= 5) && ((sc->device_id == MRSAS_TBOLT) || + (sc->mrsas_gen3_ctrl && + raid->regTypeReqOnRead != REGION_TYPE_UNUSED))) pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE; else if (raid->level == 1) { pd = MR_ArPdGet(arRef, physArm + 1, map); @@ -958,7 +959,7 @@ MR_BuildRaidContext(struct mrsas_softc *sc, struct IO_ pRAID_Context->timeoutValue = map->raidMap.fpPdIoTimeoutSec; if (sc->mrsas_gen3_ctrl) pRAID_Context->regLockFlags = (isRead) ? raid->regTypeReqOnRead : raid->regTypeReqOnWrite; - else + else if (sc->device_id == MRSAS_TBOLT) pRAID_Context->regLockFlags = (isRead) ? REGION_TYPE_SHARED_READ : raid->regTypeReqOnWrite; pRAID_Context->VirtualDiskTgtId = raid->targetId; pRAID_Context->regLockRowLBA = regStart; @@ -1478,8 +1479,9 @@ MR_GetPhyParams(struct mrsas_softc *sc, u_int32_t ld, *pDevHandle = MR_PdDevHandleGet(pd, map); else { *pDevHandle = MR_PD_INVALID; /* set dev handle as invalid. */ - if ((raid->level >= 5) && ((!sc->mrsas_gen3_ctrl) || (sc->mrsas_gen3_ctrl && - raid->regTypeReqOnRead != REGION_TYPE_UNUSED))) + if ((raid->level >= 5) && ((sc->device_id == MRSAS_TBOLT) || + (sc->mrsas_gen3_ctrl && + raid->regTypeReqOnRead != REGION_TYPE_UNUSED))) pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE; else if (raid->level == 1) { /* Get Alternate Pd. */
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