Date: Wed, 8 Mar 2000 22:48:36 -0500 From: Coleman Kane <cokane@one.net> To: Mike Smith <msmith@freebsd.org> Cc: Coleman Kane <cokane@one.net>, Roman Shterenzon <roman@ksl.co.il>, green@freebsd.org, stable@freebsd.org Subject: Re: K6-MTRRs Message-ID: <20000308224836.A37351@evil.2y.net> In-Reply-To: <200003081800.KAA03550@mass.cdrom.com>; from msmith@freebsd.org on Wed, Mar 08, 2000 at 01:02:08PM -0500 References: <20000308123838.C20193@evil.2y.net> <200003081800.KAA03550@mass.cdrom.com>
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[-- Attachment #1 --] Mike Smith had the audacity to say: > > That's the impression I was under. I have gotten no information from AMD to say > > that the MTRRs on their K6-2 line don't work. The only things I know of is that > > the first-gen chips didn't have them, and the code checks for that. Are you sure > > that it isn't some interpretation problem with the tech docs? > > If the original K6's don't have memory range registers, how could we have > tested them and discovered they didn't work? > > At any rate, you're encouraged to talk to the author/maintainer of the > code, Brian Feldman (copied). If you can make it work, wonderful. > Maybe that's it, the original K6 had them but they were "disabled" or at least ignored. I believe that the new K6-2 cores with CXT core have working MTRRs because I remember that being a big thing as well as the cache pipelining. Maybe I should get in touch with AMD on the matter as well. --cokane [-- Attachment #2 --] -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.0.0 (FreeBSD) Comment: For info see http://www.gnupg.org iD8DBQE4xx8TERViMObJ880RAc/IAKDE+DF72Xg2oNX5Yy8jKum4s5b6xACdELbL 1rqjcUcjA+1Z4UchhW5vL7w= =Z3FN -----END PGP SIGNATURE-----home | help
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