Date: Sat, 2 Aug 2008 13:04:26 +0000 (UTC) From: Scott Long <scottl@FreeBSD.org> To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org Subject: cvs commit: src/sys/dev/ciss ciss.c cissreg.h Message-ID: <200808021304.m72D4b9C016603@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
scottl 2008-08-02 13:04:26 UTC
FreeBSD src repository
Modified files:
sys/dev/ciss ciss.c cissreg.h
Log:
SVN rev 181177 on 2008-08-02 13:04:26Z by scottl
Correctly set the interrupt enable and disable bits. The previous
code interfered with Performant mode and legacy interrupts. Also
remove a register read operation on the Simplq code that was
effectively a time-wasting no-op.
Revision Changes Path
1.91 +0 -4 src/sys/dev/ciss/ciss.c
1.18 +11 -11 src/sys/dev/ciss/cissreg.h
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200808021304.m72D4b9C016603>