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Date:      Fri, 20 Nov 2020 11:26:46 +0000 (UTC)
From:      Emmanuel Vadot <manu@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r367875 - head/sys/dev/dwc
Message-ID:  <202011201126.0AKBQknE089577@repo.freebsd.org>
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Author: manu
Date: Fri Nov 20 11:26:46 2020
New Revision: 367875
URL: https://svnweb.freebsd.org/changeset/base/367875

Log:
  if_dwc: Split init code into sub function
  
  Be clear of what we enable or init.
  
  No functional changes intended

Modified:
  head/sys/dev/dwc/if_dwc.c

Modified: head/sys/dev/dwc/if_dwc.c
==============================================================================
--- head/sys/dev/dwc/if_dwc.c	Fri Nov 20 11:26:20 2020	(r367874)
+++ head/sys/dev/dwc/if_dwc.c	Fri Nov 20 11:26:46 2020	(r367875)
@@ -211,6 +211,8 @@ static void dwc_txfinish_locked(struct dwc_softc *sc);
 static void dwc_rxfinish_locked(struct dwc_softc *sc);
 static void dwc_stop_locked(struct dwc_softc *sc);
 static void dwc_setup_rxfilter(struct dwc_softc *sc);
+static void dwc_setup_core(struct dwc_softc *sc);
+static void dwc_init_dma(struct dwc_softc *sc);
 
 static inline uint32_t
 next_rxidx(struct dwc_softc *sc, uint32_t curidx)
@@ -473,7 +475,6 @@ static void
 dwc_init_locked(struct dwc_softc *sc)
 {
 	struct ifnet *ifp = sc->ifp;
-	uint32_t reg;
 
 	DWC_ASSERT_LOCKED(sc);
 
@@ -483,27 +484,9 @@ dwc_init_locked(struct dwc_softc *sc)
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 
 	dwc_setup_rxfilter(sc);
+	dwc_setup_core(sc);
+	dwc_init_dma(sc);
 
-	/* Initializa DMA and enable transmitters */
-	reg = READ4(sc, OPERATION_MODE);
-	reg |= (MODE_TSF | MODE_OSF | MODE_FUF);
-	reg &= ~(MODE_RSF);
-	reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);
-	WRITE4(sc, OPERATION_MODE, reg);
-
-	WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
-
-	/* Start DMA */
-	reg = READ4(sc, OPERATION_MODE);
-	reg |= (MODE_ST | MODE_SR);
-	WRITE4(sc, OPERATION_MODE, reg);
-
-	/* Enable transmitters */
-	reg = READ4(sc, MAC_CONFIGURATION);
-	reg |= (CONF_JD | CONF_ACS | CONF_BE);
-	reg |= (CONF_TE | CONF_RE);
-	WRITE4(sc, MAC_CONFIGURATION, reg);
-
 	/*
 	 * Call mii_mediachg() which will call back into dwc_miibus_statchg()
 	 * to set up the remaining config registers based on current media.
@@ -786,6 +769,42 @@ dwc_setup_rxfilter(struct dwc_softc *sc)
 		for (i = 0; i < nhash; i++)
 			WRITE4(sc, HASH_TABLE_REG(i), ctx.hash[i]);
 	}
+}
+
+static void
+dwc_setup_core(struct dwc_softc *sc)
+{
+	uint32_t reg;
+
+	DWC_ASSERT_LOCKED(sc);
+
+	/* Enable transmitters */
+	reg = READ4(sc, MAC_CONFIGURATION);
+	reg |= (CONF_JD | CONF_ACS | CONF_BE);
+	reg |= (CONF_TE | CONF_RE);
+	WRITE4(sc, MAC_CONFIGURATION, reg);
+}
+
+static void
+dwc_init_dma(struct dwc_softc *sc)
+{
+	uint32_t reg;
+
+	DWC_ASSERT_LOCKED(sc);
+
+	/* Initializa DMA and enable transmitters */
+	reg = READ4(sc, OPERATION_MODE);
+	reg |= (MODE_TSF | MODE_OSF | MODE_FUF);
+	reg &= ~(MODE_RSF);
+	reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);
+	WRITE4(sc, OPERATION_MODE, reg);
+
+	WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
+
+	/* Start DMA */
+	reg = READ4(sc, OPERATION_MODE);
+	reg |= (MODE_ST | MODE_SR);
+	WRITE4(sc, OPERATION_MODE, reg);
 }
 
 static int

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