Date: Sat, 21 Jul 2007 17:21:45 GMT From: Oleksandr Tymoshenko <gonzo@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 123850 for review Message-ID: <200707211721.l6LHLjqW001473@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=123850 Change 123850 by gonzo@gonzo_jeeves on 2007/07/21 17:21:07 o Move all platform-dependent code to XXX_machdep.c files o Change tick_init_params prototype, now it accept's platform timer frequency and double_count flag. o Move sysbeep to tick.c Affected files ... .. //depot/projects/mips2/src/sys/mips/include/clock.h#4 edit .. //depot/projects/mips2/src/sys/mips/mips/machdep.c#34 edit .. //depot/projects/mips2/src/sys/mips/mips/tick.c#17 edit .. //depot/projects/mips2/src/sys/mips/mips32/adm5120/adm5120_machdep.c#1 add .. //depot/projects/mips2/src/sys/mips/mips32/adm5120/files.adm5120#4 edit .. //depot/projects/mips2/src/sys/mips/mips32/malta/malta_machdep.c#2 edit .. //depot/projects/mips2/src/sys/mips/mips32/sentry5/files.sentry5#10 edit .. //depot/projects/mips2/src/sys/mips/mips32/sentry5/s5_machdep.c#2 edit Differences ... ==== //depot/projects/mips2/src/sys/mips/include/clock.h#4 (text+ko) ==== @@ -32,7 +32,13 @@ #define wall_cmos_clock 0 #define adjkerntz 0 -void tick_init_params(void); +/* + * Default is to assume a CPU pipeline clock of 100Mhz, and + * that CP0_COUNT increments every 2 cycles. + */ +#define MIPS_DEFAULT_HZ (100 * 1000 * 1000) + +void tick_init_params(uint64_t, int); void tick_init(void); int sysbeep(int pitch, int period); ==== //depot/projects/mips2/src/sys/mips/mips/machdep.c#34 (text+ko) ==== @@ -70,25 +70,14 @@ #include <machine/trap.h> #include <machine/vmparam.h> -#ifdef CFE -#include <dev/cfe/cfe_api.h> -#endif - #ifdef DDB #include <ddb/ddb.h> #endif -#ifdef CFE -extern uint32_t cfe_handle; -extern uint32_t cfe_vector; -#endif - int cold = 1; int clocks_running = 0; long realmem = 0; -extern int *edata; -extern int *end; static struct pcpu pcpu0; struct pcpu *pcpup = &pcpu0; @@ -166,82 +155,9 @@ } void -mips_init(void) +cpu_startup(void *dummy) { - int i; - - printf("entry: mips_init()\n"); - bootverbose = 0; -#ifdef CFE - /* - * Query DRAM memory map from CFE. - */ - physmem = 0; - for (i = 0; i < 10; i += 2) { - int result; - uint64_t addr, len, type; - - result = cfe_enummem(i, 0, &addr, &len, &type); - if (result < 0) { - phys_avail[i] = phys_avail[i + 1] = 0; - break; - } - if (type != CFE_MI_AVAILABLE) - continue; - - phys_avail[i] = addr; - if (i == 0 && addr == 0) { - /* - * If this is the first physical memory segment probed - * from CFE, omit the region at the start of physical - * memory where the kernel has been loaded. - */ - phys_avail[i] += MIPS_KSEG0_TO_PHYS((vm_offset_t)&end); - } - phys_avail[i + 1] = addr + len; - physmem += len; - } - - realmem = btoc(physmem); -#else /* !CFE */ - realmem = btoc(64 << 20); - - for (i = 0; i < 10; i++) { - phys_avail[i] = 0; - } - - /* phys_avail regions are in bytes */ - phys_avail[0] = MIPS_KSEG0_TO_PHYS((vm_offset_t)&end); - phys_avail[1] = ctob(realmem); -#endif - - physmem = realmem; - - init_param1(); - init_param2(physmem); - - /* XXX: Catch 22. Something touches the tlb. */ - mips_cpu_init(); - pmap_bootstrap(); - - proc_linkup(&proc0, &thread0); - thread0.td_kstack = kstack0; - pcpu_init(pcpup, 0, sizeof(struct pcpu)); - pcpup->pc_curthread = &thread0; - cpu_thread_setup(curthread); - pcpup->pc_curpcb = curthread->td_pcb; - - mutex_init(); - -#ifdef DDB - kdb_init(); -#endif -} - -void -cpu_startup(void *dummy) -{ cpu_identify(); platform_identify(); vm_ksubmap_init(&kmi); @@ -253,12 +169,14 @@ int cpu_est_clockrate(int cpu_id, uint64_t *rate) { + return (ENXIO); } void cpu_halt(void) { + printf("Halting...\n"); platform_halt(); } @@ -385,6 +303,7 @@ int fill_regs(struct thread *td, struct reg *regs) { + __asm __volatile("break"); return (0); } @@ -392,6 +311,7 @@ int fill_dbregs(struct thread *td, struct dbreg *dbregs) { + __asm __volatile("break"); return (0); } @@ -399,12 +319,14 @@ int fill_fpregs(struct thread *td, struct fpreg *fpregs) { + return (0); } int set_regs(struct thread *td, struct reg *regs) { + __asm __volatile("break"); return (0); } @@ -412,36 +334,42 @@ int set_dbregs(struct thread *td, struct dbreg *dbregs) { + return (0); } int set_fpregs(struct thread *td, struct fpreg *fpregs) { + return (0); } int ptrace_set_pc(struct thread *td, u_long addr) { + return (0); } int ptrace_clear_single_step(struct thread *td) { + return (0); } int ptrace_single_step(struct thread *td) { + return (0); } void cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz) { + } void @@ -452,8 +380,8 @@ tf->tf_regs[TF_EPC] = (register_t)entry; tf->tf_regs[TF_SP] = (register_t)stack; tf->tf_regs[TF_SR] |= MIPS_SR_KSU_USER; + tf->tf_regs[TF_SR] |= MIPS_SR_EXL; tf->tf_regs[TF_SR] |= MIPS_SR_COP_0_BIT; - tf->tf_regs[TF_SR] |= MIPS_SR_EXL; tf->tf_regs[TF_T9] = (register_t)entry; /* Used by PIC code */ } @@ -481,68 +409,6 @@ intr_restore(td->td_md.md_saved_sr); } -void -platform_halt(void) -{ - -} - - -void -platform_identify(void) -{ - -} - -void -platform_reset(void) -{ - -#if defined(CFE) - cfe_exit(0, 0); -#endif -} - -void -platform_trap_enter(void) -{ - -} - -void -platform_trap_exit(void) -{ - -} - -void -platform_start(int argc, char **argv) -{ - vm_offset_t kernend; - - /* clear the BSS and SBSS segments */ - kernend = round_page((vm_offset_t)&end); - memset(&edata, 0, kernend - (vm_offset_t)(&edata)); - -#ifdef CFE - /* - * Initialize CFE firmware trampolines before - * we initialize the low-level console. - */ - if (cfe_handle != 0) - cfe_init(cfe_handle, cfe_vector); -#endif - cninit(); - -#ifdef CFE - if (cfe_handle == 0) - panic("CFE was not detected by locore.\n"); -#endif - - mips_init(); - tick_init_params(); -} - void setPQL2(int *const size, int *const ways); void @@ -602,12 +468,4 @@ } -/* - * XXX Needed by syscons - */ -int -sysbeep(int pitch, int period) -{ - return (0); -} ==== //depot/projects/mips2/src/sys/mips/mips/tick.c#17 (text+ko) ==== @@ -49,28 +49,6 @@ #include <machine/locore.h> #include <machine/md_var.h> -#ifdef TICK_USE_YAMON_FREQ -#include <mips/mips4k/malta/yamon.h> -#endif - -#ifdef TICK_USE_MALTA_RTC -#include <mips/mips4k/malta/maltareg.h> -#include <dev/mc146818/mc146818reg.h> -#include <isa/rtc.h> -#endif - -#ifdef CPU_SENTRY5 -#include <machine/cpuregs.h> -#include <mips/mips32/sentry5/s5reg.h> -#endif - -/* - * Default is to assume a CPU pipeline clock of 100Mhz, and - * that CP0_COUNT increments every 2 cycles. - */ -#define MIPS_DEFAULT_HZ (100 * 1000 * 1000) -#define MIPS_DOUBLE_COUNT 1 - uint64_t counter_freq; uint64_t counts_per_hz; uint32_t counts_per_usec; @@ -94,28 +72,6 @@ 800, /* quality (adjusted in code) */ }; -#ifdef TICK_USE_MALTA_RTC -static __inline uint8_t -rtcin(uint8_t addr) -{ - - *((volatile uint8_t *) - MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCADR))) = addr; - return (*((volatile uint8_t *) - MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCDAT)))); -} - -static __inline void -writertc(uint8_t addr, uint8_t val) -{ - - *((volatile uint8_t *) - MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCADR))) = addr; - *((volatile uint8_t *) - MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCDAT))) = val; -} -#endif - static uint64_t tick_ticker(void) { @@ -124,89 +80,11 @@ } void -tick_init_params(void) +tick_init_params(uint64_t platform_counter_freq, int double_count) { - if (bootverbose) - printf("Calibrating MIPS32 clock ... "); - - do { -#if defined(TICK_USE_YAMON_FREQ) - /* - * If we are running on a board which uses YAMON firmware, - * then query CPU pipeline clock from the syscon object. - * If unsuccessful, use hard-coded default. - */ - counter_freq = yamon_getcpufreq(); - if (counter_freq == 0) { - counter_freq = MIPS_DEFAULT_HZ; - } -#elif defined(TICK_USE_MALTA_RTC) - /* - * If we are running on a board with the MC146818 RTC, - * use it to determine CPU pipeline clock frequency. - */ - u_int64_t counterval[2]; - - /* Set RTC to binary mode. */ - writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD)); - - /* Busy-wait for falling edge of RTC update. */ - while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0)) - ; - while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0)) - ; - counterval[0] = mips_rd_count(); - - /* Busy-wait for falling edge of RTC update. */ - while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0)) - ; - while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0)) - ; - counterval[1] = mips_rd_count(); + counter_freq = platform_counter_freq; - counter_freq = counterval[1] - counterval[0]; -#elif defined(CPU_SENTRY5) -# if 0 - /* - * Probe the Broadcom Sentry5's on-chip PLL clock registers - * and discover the CPU pipeline clock and bus clock - * multipliers from this. - * XXX: Wrong place. You have to ask the ChipCommon - * or External Interface cores on the SiBa. - */ - uint32_t busmult, cpumult, refclock, clkcfg1; -#define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F -#define S5_CLKCFG1_BUSMULT_MASK 0x000003E0 -#define S5_CLKCFG1_BUSMULT_SHIFT 5 -#define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00 -#define S5_CLKCFG1_CPUMULT_SHIFT 10 - - counter_freq = 100000000; /* XXX */ - - clkcfg1 = s5_rd_clkcfg1(); - printf("clkcfg1 = 0x%08x\n", clkcfg1); - - refclock = clkcfg1 & 0x1F; - busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1; - cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1; - - printf("refclock = %u\n", refclock); - printf("busmult = %u\n", busmult); - printf("cpumult = %u\n", cpumult); - - counter_freq = cpumult * refclock; -# else - counter_freq = 200 * 1000 * 1000; /* Sentry5 is 200MHz */ -# endif -#else - /* - * Use a completely fictional hardcoded default. - */ - counter_freq = MIPS_DEFAULT_HZ; -#endif - } while (0); - counts_per_hz = counter_freq / hz; counts_per_usec = counter_freq / (1 * 1000 * 1000); @@ -214,13 +92,12 @@ * XXX: Some MIPS32 cores update the Count register * only every two pipeline cycles. */ - if (MIPS_DOUBLE_COUNT != 0) { + if (double_count != 0) { counts_per_hz /= 2; counts_per_usec /= 2; } printf("MIPS32 clock: %ju Hz\n", (intmax_t)counter_freq); - set_cputicker(tick_ticker, counter_freq, 1); } @@ -266,7 +143,6 @@ void DELAY(int n) { -#ifndef CPU_SENTRY5 /* TODO: Fix clock calibration for this board */ uint32_t cur, last, delta, usecs; /* * This works by polling the timer and counting the @@ -291,7 +167,13 @@ delta %= counts_per_usec; } } -#endif +} + +int +sysbeep(int pitch, int period) +{ + + return (0); } /* ==== //depot/projects/mips2/src/sys/mips/mips32/adm5120/files.adm5120#4 (text+ko) ==== @@ -2,9 +2,10 @@ # ADM5120 on-board devices # mips/mips32/adm5120/console.c standard -mips/mips32/adm5120/obio.c standard +mips/mips32/adm5120/adm5120_machdep.c standard mips/mips32/adm5120/admpci.c optional admpci mips/mips32/adm5120/if_admsw.c optional admsw +mips/mips32/adm5120/obio.c standard mips/mips32/adm5120/uart_bus_adm5120.c optional uart mips/mips32/adm5120/uart_cpu_adm5120.c optional uart mips/mips32/adm5120/uart_dev_adm5120.c optional uart ==== //depot/projects/mips2/src/sys/mips/mips32/malta/malta_machdep.c#2 (text+ko) ==== @@ -29,11 +29,55 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> +#include <sys/conf.h> +#include <sys/kernel.h> +#include <sys/systm.h> +#include <sys/imgact.h> +#include <sys/bio.h> +#include <sys/buf.h> +#include <sys/bus.h> +#include <sys/cpu.h> +#include <sys/cons.h> +#include <sys/exec.h> +#include <sys/ucontext.h> +#include <sys/proc.h> +#include <sys/kdb.h> +#include <sys/ptrace.h> +#include <sys/reboot.h> +#include <sys/signalvar.h> +#include <sys/sysent.h> +#include <sys/sysproto.h> +#include <sys/user.h> + +#include <vm/vm.h> +#include <vm/vm_object.h> +#include <vm/vm_page.h> +#include <vm/vm_pager.h> + +#include <machine/clock.h> #include <machine/cpuregs.h> +#include <machine/hwfunc.h> +#include <machine/md_var.h> +#include <machine/pmap.h> +#include <machine/trap.h> + +#ifdef TICK_USE_YAMON_FREQ +#include <mips/mips32/malta/yamon.h> +#endif + +#ifdef TICK_USE_MALTA_RTC +#include <mips/mips4k/malta/maltareg.h> +#include <dev/mc146818/mc146818reg.h> +#include <isa/rtc.h> +#endif + #include <mips/mips32/malta/maltareg.h> -void lcd_init(void); -void lcd_puts(char *); +extern int *edata; +extern int *end; + +void lcd_init(void); +void lcd_puts(char *); void malta_reset(void); /* @@ -93,15 +137,157 @@ malta_lcd_print(s); } +#ifdef TICK_USE_MALTA_RTC +static __inline uint8_t +rtcin(uint8_t addr) +{ + + *((volatile uint8_t *) + MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCADR))) = addr; + return (*((volatile uint8_t *) + MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCDAT)))); +} + +static __inline void +writertc(uint8_t addr, uint8_t val) +{ + + *((volatile uint8_t *) + MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCADR))) = addr; + *((volatile uint8_t *) + MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCDAT))) = val; +} +#endif + +void +mips_init(void) +{ + int i; + + printf("entry: mips_init()\n"); + + bootverbose = 1; + realmem = btoc(16 << 20); + + for (i = 0; i < 10; i++) { + phys_avail[i] = 0; + } + + /* phys_avail regions are in bytes */ + phys_avail[0] = MIPS_KSEG0_TO_PHYS((vm_offset_t)&end); + phys_avail[1] = ctob(realmem); + + physmem = realmem; + + init_param1(); + init_param2(physmem); + + mips_cpu_init(); + pmap_bootstrap(); + + proc_linkup(&proc0, &thread0); + thread0.td_kstack = kstack0; + pcpu_init(pcpup, 0, sizeof(struct pcpu)); + pcpup->pc_curthread = &thread0; + cpu_thread_setup(curthread); + pcpup->pc_curpcb = curthread->td_pcb; + + mutex_init(); + +#ifdef DDB + kdb_init(); +#endif +} + +void +platform_halt(void) +{ + +} + + +void +platform_identify(void) +{ + +} + /* * Perform a board-level soft-reset. * Note that this is not emulated by gxemul. */ void -malta_reset(void) +platform_reset(void) { char *c; c = (char *)MIPS_PHYS_TO_KSEG0(MALTA_SOFTRES); *c = MALTA_GORESET; } + +void +platform_trap_enter(void) +{ + +} + +void +platform_trap_exit(void) +{ + +} + +void +platform_start(int argc, char **argv) +{ + vm_offset_t kernend; + uint64_t platform_counter_freq; + + /* clear the BSS and SBSS segments */ + kernend = round_page((vm_offset_t)&end); + memset(&edata, 0, kernend - (vm_offset_t)(&edata)); + + cninit(); + + mips_init(); + do { +#if defined(TICK_USE_YAMON_FREQ) + /* + * If we are running on a board which uses YAMON firmware, + * then query CPU pipeline clock from the syscon object. + * If unsuccessful, use hard-coded default. + */ + platform_counter_freq = yamon_getcpufreq(); + if (platform_counter_freq == 0) + platform_counter_freq = MIPS_DEFAULT_HZ; + +#elif defined(TICK_USE_MALTA_RTC) + /* + * If we are running on a board with the MC146818 RTC, + * use it to determine CPU pipeline clock frequency. + */ + u_int64_t counterval[2]; + + /* Set RTC to binary mode. */ + writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD)); + + /* Busy-wait for falling edge of RTC update. */ + while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0)) + ; + while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0)) + ; + counterval[0] = mips_rd_count(); + + /* Busy-wait for falling edge of RTC update. */ + while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0)) + ; + while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0)) + ; + counterval[1] = mips_rd_count(); + + platform_counter_freq = counterval[1] - counterval[0]; +#endif + } while(0); + + tick_init_params(platform_counter_freq, 0); +} ==== //depot/projects/mips2/src/sys/mips/mips32/sentry5/files.sentry5#10 (text+ko) ==== @@ -5,10 +5,10 @@ # which are believed to be devices we have drivers for # which just need to be tweaked for attachment to an SSB system bus. +mips/mips32/sentry5/s5_machdep.c standard dev/siba/siba.c optional siba dev/siba/siba_pcib.c optional siba pci mips/mips32/sentry5/siba_cc.c optional siba -#mips/mips32/sentry5/s5_machdep.c standard # notyet #mips/mips32/sentry5/siba_mips.c optional siba ==== //depot/projects/mips2/src/sys/mips/mips32/sentry5/s5_machdep.c#2 (text+ko) ==== @@ -30,13 +30,220 @@ #include <sys/param.h> #include <machine/cpuregs.h> -#include <mips/mips32/sentry5/sentry5reg.h> +#include <mips/mips32/sentry5/s5reg.h> + +#include "opt_ddb.h" + +#include <sys/param.h> +#include <sys/conf.h> +#include <sys/kernel.h> +#include <sys/systm.h> +#include <sys/imgact.h> +#include <sys/bio.h> +#include <sys/buf.h> +#include <sys/bus.h> +#include <sys/cpu.h> +#include <sys/cons.h> +#include <sys/exec.h> +#include <sys/ucontext.h> +#include <sys/proc.h> +#include <sys/kdb.h> +#include <sys/ptrace.h> +#include <sys/reboot.h> +#include <sys/signalvar.h> +#include <sys/sysent.h> +#include <sys/sysproto.h> +#include <sys/user.h> + +#include <vm/vm.h> +#include <vm/vm_object.h> +#include <vm/vm_page.h> +#include <vm/vm_pager.h> + +#include <machine/cache.h> +#include <machine/clock.h> +#include <machine/cpu.h> +#include <machine/cpuinfo.h> +#include <machine/cpufunc.h> +#include <machine/cpuregs.h> +#include <machine/hwfunc.h> +#include <machine/intr_machdep.h> +#include <machine/locore.h> +#include <machine/md_var.h> +#include <machine/pte.h> +#include <machine/sigframe.h> +#include <machine/tlb.h> +#include <machine/trap.h> +#include <machine/vmparam.h> + +#ifdef CFE +#include <dev/cfe/cfe_api.h> +#endif + +#ifdef CFE +extern uint32_t cfe_handle; +extern uint32_t cfe_vector; +#endif + +extern int *edata; +extern int *end; + +void +mips_init(void) +{ + int i; + + printf("entry: mips_init()\n"); + +#ifdef CFE + /* + * Query DRAM memory map from CFE. + */ + physmem = 0; + for (i = 0; i < 10; i += 2) { + int result; + uint64_t addr, len, type; + + result = cfe_enummem(i, 0, &addr, &len, &type); + if (result < 0) { + phys_avail[i] = phys_avail[i + 1] = 0; + break; + } + if (type != CFE_MI_AVAILABLE) + continue; + + phys_avail[i] = addr; + if (i == 0 && addr == 0) { + /* + * If this is the first physical memory segment probed + * from CFE, omit the region at the start of physical + * memory where the kernel has been loaded. + */ + phys_avail[i] += MIPS_KSEG0_TO_PHYS((vm_offset_t)&end); + } + phys_avail[i + 1] = addr + len; + physmem += len; + } + + realmem = btoc(physmem); +#endif + + physmem = realmem; + + init_param1(); + init_param2(physmem); + + mips_cpu_init(); + pmap_bootstrap(); + + proc_linkup(&proc0, &thread0); + thread0.td_kstack = kstack0; + pcpu_init(pcpup, 0, sizeof(struct pcpu)); + pcpup->pc_curthread = &thread0; + cpu_thread_setup(curthread); + pcpup->pc_curpcb = curthread->td_pcb; + + mutex_init(); + +#ifdef DDB + kdb_init(); +#endif +} + +void +platform_halt(void) +{ + +} + + +void +platform_identify(void) +{ -void sentry5_reset(void); +} void -sentry5_reset(void) +platform_reset(void) { +#if defined(CFE) + cfe_exit(0, 0); +#else *((volatile uint8_t *)MIPS_PHYS_TO_KSEG1(SENTRY5_EXTIFADR)) = 0x80; +#endif +} + +void +platform_trap_enter(void) +{ + +} + +void +platform_trap_exit(void) +{ + +} + +void +platform_start(int argc, char **argv) +{ + vm_offset_t kernend; + uint64_t platform_counter_freq; + + /* clear the BSS and SBSS segments */ + kernend = round_page((vm_offset_t)&end); + memset(&edata, 0, kernend - (vm_offset_t)(&edata)); + +#ifdef CFE + /* + * Initialize CFE firmware trampolines before + * we initialize the low-level console. + */ + if (cfe_handle != 0) + cfe_init(cfe_handle, cfe_vector); +#endif + cninit(); + +#ifdef CFE + if (cfe_handle == 0) + panic("CFE was not detected by locore.\n"); +#endif + mips_init(); + +# if 0 + /* + * Probe the Broadcom Sentry5's on-chip PLL clock registers + * and discover the CPU pipeline clock and bus clock + * multipliers from this. + * XXX: Wrong place. You have to ask the ChipCommon + * or External Interface cores on the SiBa. + */ + uint32_t busmult, cpumult, refclock, clkcfg1; +#define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F +#define S5_CLKCFG1_BUSMULT_MASK 0x000003E0 +#define S5_CLKCFG1_BUSMULT_SHIFT 5 +#define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00 +#define S5_CLKCFG1_CPUMULT_SHIFT 10 + + counter_freq = 100000000; /* XXX */ + + clkcfg1 = s5_rd_clkcfg1(); + printf("clkcfg1 = 0x%08x\n", clkcfg1); + + refclock = clkcfg1 & 0x1F; + busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1; + cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1; + + printf("refclock = %u\n", refclock); + printf("busmult = %u\n", busmult); + printf("cpumult = %u\n", cpumult); + + counter_freq = cpumult * refclock; +# else + platform_counter_freq = 200 * 1000 * 1000; /* Sentry5 is 200MHz */ +# endif + + tick_init_params(platform_counter_freq, 0); }help
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