Date: Thu, 28 Dec 2023 03:26:09 GMT From: Warner Losh <imp@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 4654e8a3bff5 - main - ciss: Fix typo (triple T) Message-ID: <202312280326.3BS3Q9uj077484@gitrepo.freebsd.org>
next in thread | raw e-mail | index | archive | help
The branch main has been updated by imp: URL: https://cgit.FreeBSD.org/src/commit/?id=4654e8a3bff5310801d59c7bb296a72c5fe8ec7c commit 4654e8a3bff5310801d59c7bb296a72c5fe8ec7c Author: Jose Luis Duran <jlduran@gmail.com> AuthorDate: 2023-12-28 03:17:07 +0000 Commit: Warner Losh <imp@FreeBSD.org> CommitDate: 2023-12-28 03:24:30 +0000 ciss: Fix typo (triple T) Reviewed by: imp Pull Request: https://github.com/freebsd/freebsd-src/pull/954 --- sys/dev/ciss/cissreg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/dev/ciss/cissreg.h b/sys/dev/ciss/cissreg.h index b9dc10fbf478..9e7434b74291 100644 --- a/sys/dev/ciss/cissreg.h +++ b/sys/dev/ciss/cissreg.h @@ -684,7 +684,7 @@ struct ciss_bmic_id_table { u_int8_t percent_write_cache; /* Percent of memory allocated to write cache */ u_int16_t daughterboard_size_mb; /* Total size (MB) of cache board */ u_int8_t cache_batter_count; /* Number of cache batteries */ - u_int16_t total_controller_mem_mb; /* Total size (MB) of atttached memory */ + u_int16_t total_controller_mem_mb; /* Total size (MB) of attached memory */ u_int8_t more_controller_flags; /* Additional controller flags byte */ u_int8_t x_board_host_i2c_rev; /* 2nd byte of 3 byte autorev field */ u_int8_t battery_pic_rev; /* BBWC PIC revision */
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?202312280326.3BS3Q9uj077484>