Date: Wed, 1 Feb 2017 21:57:08 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r313067 - in projects/clang400-import: contrib/libc++/include contrib/llvm/include/llvm/CodeGen contrib/llvm/lib/CodeGen contrib/llvm/lib/CodeGen/AsmPrinter contrib/llvm/lib/CodeGen/Sel... Message-ID: <201702012157.v11Lv8b8009851@repo.freebsd.org>
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Author: dim Date: Wed Feb 1 21:57:07 2017 New Revision: 313067 URL: https://svnweb.freebsd.org/changeset/base/313067 Log: Merge llvm, clang, compiler-rt, libc++, lld and lldb release_40 branch r293807, and update build glue. Modified: projects/clang400-import/contrib/libc++/include/mutex projects/clang400-import/contrib/llvm/include/llvm/CodeGen/AsmPrinter.h projects/clang400-import/contrib/llvm/include/llvm/CodeGen/SelectionDAGISel.h projects/clang400-import/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp projects/clang400-import/contrib/llvm/lib/CodeGen/AsmPrinter/DIE.cpp projects/clang400-import/contrib/llvm/lib/CodeGen/InterleavedAccessPass.cpp projects/clang400-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp projects/clang400-import/contrib/llvm/lib/MC/MCMachOStreamer.cpp projects/clang400-import/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp projects/clang400-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h projects/clang400-import/contrib/llvm/lib/Target/Mips/MicroMipsInstrFPU.td projects/clang400-import/contrib/llvm/lib/Target/Mips/MicroMipsInstrFormats.td projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.cpp projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.h projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.h projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCSchedule.td projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCScheduleE5500.td projects/clang400-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp projects/clang400-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp projects/clang400-import/contrib/llvm/lib/Transforms/Scalar/SCCP.cpp projects/clang400-import/contrib/llvm/tools/clang/include/clang/AST/Type.h projects/clang400-import/contrib/llvm/tools/clang/include/clang/Basic/DiagnosticSemaKinds.td projects/clang400-import/contrib/llvm/tools/clang/include/clang/Sema/Overload.h projects/clang400-import/contrib/llvm/tools/clang/include/clang/Sema/Sema.h projects/clang400-import/contrib/llvm/tools/clang/lib/AST/ExprConstant.cpp projects/clang400-import/contrib/llvm/tools/clang/lib/CodeGen/CodeGenTypes.cpp projects/clang400-import/contrib/llvm/tools/clang/lib/Sema/SemaChecking.cpp projects/clang400-import/contrib/llvm/tools/clang/lib/Sema/SemaExpr.cpp projects/clang400-import/contrib/llvm/tools/clang/lib/Sema/SemaExprCXX.cpp projects/clang400-import/contrib/llvm/tools/clang/lib/Sema/SemaLookup.cpp projects/clang400-import/contrib/llvm/tools/clang/lib/Sema/SemaOverload.cpp projects/clang400-import/contrib/llvm/tools/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp projects/clang400-import/contrib/llvm/tools/clang/lib/Sema/TreeTransform.h projects/clang400-import/contrib/llvm/tools/lld/ELF/InputFiles.h projects/clang400-import/contrib/llvm/tools/lld/ELF/InputSection.cpp projects/clang400-import/contrib/llvm/tools/lld/ELF/SyntheticSections.cpp projects/clang400-import/contrib/llvm/tools/lld/ELF/SyntheticSections.h projects/clang400-import/contrib/llvm/tools/lld/ELF/Writer.cpp projects/clang400-import/lib/clang/include/clang/Basic/Version.inc projects/clang400-import/lib/clang/include/lld/Config/Version.inc Directory Properties: projects/clang400-import/contrib/compiler-rt/ (props changed) projects/clang400-import/contrib/libc++/ (props changed) projects/clang400-import/contrib/llvm/ (props changed) projects/clang400-import/contrib/llvm/tools/clang/ (props changed) projects/clang400-import/contrib/llvm/tools/lld/ (props changed) projects/clang400-import/contrib/llvm/tools/lldb/ (props changed) Modified: projects/clang400-import/contrib/libc++/include/mutex ============================================================================== --- projects/clang400-import/contrib/libc++/include/mutex Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/libc++/include/mutex Wed Feb 1 21:57:07 2017 (r313067) @@ -559,7 +559,6 @@ public: #endif template <class _Fp> -inline _LIBCPP_INLINE_VISIBILITY void __call_once_proxy(void* __vp) { Modified: projects/clang400-import/contrib/llvm/include/llvm/CodeGen/AsmPrinter.h ============================================================================== --- projects/clang400-import/contrib/llvm/include/llvm/CodeGen/AsmPrinter.h Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/include/llvm/CodeGen/AsmPrinter.h Wed Feb 1 21:57:07 2017 (r313067) @@ -480,6 +480,12 @@ public: /// Get the value for DW_AT_APPLE_isa. Zero if no isa encoding specified. virtual unsigned getISAEncoding() { return 0; } + /// Emit the directive and value for debug thread local expression + /// + /// \p Value - The value to emit. + /// \p Size - The size of the integer (in bytes) to emit. + virtual void EmitDebugValue(const MCExpr *Value, unsigned Size) const; + //===------------------------------------------------------------------===// // Dwarf Lowering Routines //===------------------------------------------------------------------===// Modified: projects/clang400-import/contrib/llvm/include/llvm/CodeGen/SelectionDAGISel.h ============================================================================== --- projects/clang400-import/contrib/llvm/include/llvm/CodeGen/SelectionDAGISel.h Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/include/llvm/CodeGen/SelectionDAGISel.h Wed Feb 1 21:57:07 2017 (r313067) @@ -305,7 +305,7 @@ private: std::vector<unsigned> OpcodeOffset; void UpdateChains(SDNode *NodeToMatch, SDValue InputChain, - const SmallVectorImpl<SDNode *> &ChainNodesMatched, + SmallVectorImpl<SDNode *> &ChainNodesMatched, bool isMorphNodeTo); }; Modified: projects/clang400-import/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -567,6 +567,15 @@ void AsmPrinter::EmitGlobalVariable(cons OutStreamer->AddBlankLine(); } +/// Emit the directive and value for debug thread local expression +/// +/// \p Value - The value to emit. +/// \p Size - The size of the integer (in bytes) to emit. +void AsmPrinter::EmitDebugValue(const MCExpr *Value, + unsigned Size) const { + OutStreamer->EmitValue(Value, Size); +} + /// EmitFunctionHeader - This method emits the header for the current /// function. void AsmPrinter::EmitFunctionHeader() { Modified: projects/clang400-import/contrib/llvm/lib/CodeGen/AsmPrinter/DIE.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/CodeGen/AsmPrinter/DIE.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/CodeGen/AsmPrinter/DIE.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -484,7 +484,7 @@ void DIEInteger::print(raw_ostream &O) c /// EmitValue - Emit expression value. /// void DIEExpr::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const { - AP->OutStreamer->EmitValue(Expr, SizeOf(AP, Form)); + AP->EmitDebugValue(Expr, SizeOf(AP, Form)); } /// SizeOf - Determine size of expression value in bytes. Modified: projects/clang400-import/contrib/llvm/lib/CodeGen/InterleavedAccessPass.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/CodeGen/InterleavedAccessPass.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/CodeGen/InterleavedAccessPass.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -174,7 +174,7 @@ static bool isDeInterleaveMask(ArrayRef< /// I.e. <0, LaneLen, ... , LaneLen*(Factor - 1), 1, LaneLen + 1, ...> /// E.g. For a Factor of 2 (LaneLen=4): <0, 4, 1, 5, 2, 6, 3, 7> static bool isReInterleaveMask(ArrayRef<int> Mask, unsigned &Factor, - unsigned MaxFactor) { + unsigned MaxFactor, unsigned OpNumElts) { unsigned NumElts = Mask.size(); if (NumElts < 4) return false; @@ -246,6 +246,9 @@ static bool isReInterleaveMask(ArrayRef< if (StartMask < 0) break; + // We must stay within the vectors; This case can happen with undefs. + if (StartMask + LaneLen > OpNumElts*2) + break; } // Found an interleaved mask of current factor. @@ -406,7 +409,8 @@ bool InterleavedAccess::lowerInterleaved // Check if the shufflevector is RE-interleave shuffle. unsigned Factor; - if (!isReInterleaveMask(SVI->getShuffleMask(), Factor, MaxFactor)) + unsigned OpNumElts = SVI->getOperand(0)->getType()->getVectorNumElements(); + if (!isReInterleaveMask(SVI->getShuffleMask(), Factor, MaxFactor, OpNumElts)) return false; DEBUG(dbgs() << "IA: Found an interleaved store: " << *SI << "\n"); Modified: projects/clang400-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -2248,7 +2248,7 @@ GetVBR(uint64_t Val, const unsigned char /// to use the new results. void SelectionDAGISel::UpdateChains( SDNode *NodeToMatch, SDValue InputChain, - const SmallVectorImpl<SDNode *> &ChainNodesMatched, bool isMorphNodeTo) { + SmallVectorImpl<SDNode *> &ChainNodesMatched, bool isMorphNodeTo) { SmallVector<SDNode*, 4> NowDeadNodes; // Now that all the normal results are replaced, we replace the chain and @@ -2260,6 +2260,11 @@ void SelectionDAGISel::UpdateChains( // Replace all the chain results with the final chain we ended up with. for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { SDNode *ChainNode = ChainNodesMatched[i]; + // If ChainNode is null, it's because we replaced it on a previous + // iteration and we cleared it out of the map. Just skip it. + if (!ChainNode) + continue; + assert(ChainNode->getOpcode() != ISD::DELETED_NODE && "Deleted node left in chain"); @@ -2272,6 +2277,11 @@ void SelectionDAGISel::UpdateChains( if (ChainVal.getValueType() == MVT::Glue) ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); + SelectionDAG::DAGNodeDeletedListener NDL( + *CurDAG, [&](SDNode *N, SDNode *E) { + std::replace(ChainNodesMatched.begin(), ChainNodesMatched.end(), N, + static_cast<SDNode *>(nullptr)); + }); CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); // If the node became dead and we haven't already seen it, delete it. Modified: projects/clang400-import/contrib/llvm/lib/MC/MCMachOStreamer.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/MC/MCMachOStreamer.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/MC/MCMachOStreamer.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -142,7 +142,8 @@ static bool canGoAfterDWARF(const MCSect if (SegName == "__TEXT" && SecName == "__eh_frame") return true; - if (SegName == "__DATA" && SecName == "__nl_symbol_ptr") + if (SegName == "__DATA" && (SecName == "__nl_symbol_ptr" || + SecName == "__thread_ptr")) return true; return false; Modified: projects/clang400-import/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -413,6 +413,7 @@ public: Match_RequiresDifferentOperands, Match_RequiresNoZeroRegister, Match_RequiresSameSrcAndDst, + Match_NoFCCRegisterForCurrentISA, Match_NonZeroOperandForSync, #define GET_OPERAND_DIAGNOSTIC_TYPES #include "MipsGenAsmMatcher.inc" @@ -1461,8 +1462,6 @@ public: bool isFCCAsmReg() const { if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC)) return false; - if (!AsmParser.hasEightFccRegisters()) - return RegIdx.Index == 0; return RegIdx.Index <= 7; } bool isACCAsmReg() const { @@ -4053,6 +4052,7 @@ MipsAsmParser::checkEarlyTargetMatchPred return Match_RequiresSameSrcAndDst; } } + unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { switch (Inst.getOpcode()) { // As described by the MIPSR6 spec, daui must not use the zero operand for @@ -4131,9 +4131,15 @@ unsigned MipsAsmParser::checkTargetMatch if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) return Match_RequiresDifferentOperands; return Match_Success; - default: - return Match_Success; } + + uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags; + if ((TSFlags & MipsII::HasFCCRegOperand) && + (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters()) + return Match_NoFCCRegisterForCurrentISA; + + return Match_Success; + } static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands, @@ -4191,6 +4197,9 @@ bool MipsAsmParser::MatchAndEmitInstruct return Error(IDLoc, "invalid operand ($zero) for instruction"); case Match_RequiresSameSrcAndDst: return Error(IDLoc, "source and destination must match"); + case Match_NoFCCRegisterForCurrentISA: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "non-zero fcc register doesn't exist in current ISA level"); case Match_Immz: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'"); case Match_UImm1_0: Modified: projects/clang400-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h Wed Feb 1 21:57:07 2017 (r313067) @@ -123,7 +123,9 @@ namespace MipsII { HasForbiddenSlot = 1 << 5, /// IsPCRelativeLoad - A Load instruction with implicit source register /// ($pc) with explicit offset and destination register - IsPCRelativeLoad = 1 << 6 + IsPCRelativeLoad = 1 << 6, + /// HasFCCRegOperand - Instruction uses an $fcc<x> register. + HasFCCRegOperand = 1 << 7 }; } Modified: projects/clang400-import/contrib/llvm/lib/Target/Mips/MicroMipsInstrFPU.td ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/Mips/MicroMipsInstrFPU.td Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/Mips/MicroMipsInstrFPU.td Wed Feb 1 21:57:07 2017 (r313067) @@ -27,9 +27,20 @@ def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6; def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, - CEQS_FM_MM<0>; + CEQS_FM_MM<0> { + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; +} + def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, - CEQS_FM_MM<1>; + CEQS_FM_MM<1> { + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; +} def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>, BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6; @@ -164,6 +175,98 @@ let AdditionalPredicates = [InMicroMips] def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>, LW_FM_MM<0x26>; } + + multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt, + InstrItinClass itin> { + def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 0> { + let BaseOpcode = "c.f."#NAME; + let isCommutable = 1; + } + def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 1> { + let BaseOpcode = "c.un."#NAME; + let isCommutable = 1; + } + def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 2> { + let BaseOpcode = "c.eq."#NAME; + let isCommutable = 1; + } + def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 3> { + let BaseOpcode = "c.ueq."#NAME; + let isCommutable = 1; + } + def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 4> { + let BaseOpcode = "c.olt."#NAME; + } + def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 5> { + let BaseOpcode = "c.ult."#NAME; + } + def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 6> { + let BaseOpcode = "c.ole."#NAME; + } + def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 7> { + let BaseOpcode = "c.ule."#NAME; + } + def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 8> { + let BaseOpcode = "c.sf."#NAME; + let isCommutable = 1; + } + def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 9> { + let BaseOpcode = "c.ngle."#NAME; + } + def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 10> { + let BaseOpcode = "c.seq."#NAME; + let isCommutable = 1; + } + def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 11> { + let BaseOpcode = "c.ngl."#NAME; + } + def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 12> { + let BaseOpcode = "c.lt."#NAME; + } + def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 13> { + let BaseOpcode = "c.nge."#NAME; + } + def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 14> { + let BaseOpcode = "c.le."#NAME; + } + def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 15> { + let BaseOpcode = "c.ngt."#NAME; + } + } + + defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>, + ISA_MIPS1_NOT_32R6_64R6; + defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>, + ISA_MIPS1_NOT_32R6_64R6, FGR_32; + let DecoderNamespace = "Mips64" in + defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>, + ISA_MIPS1_NOT_32R6_64R6, FGR_64; + + defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6; + defm D32_MM : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_32; + defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_64; + + defm : BC1_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">, + ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; } //===----------------------------------------------------------------------===// Modified: projects/clang400-import/contrib/llvm/lib/Target/Mips/MicroMipsInstrFormats.td ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/Mips/MicroMipsInstrFormats.td Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/Mips/MicroMipsInstrFormats.td Wed Feb 1 21:57:07 2017 (r313067) @@ -766,6 +766,7 @@ class SWXC1_FM_MM<bits<9> funct> : MMArc class CEQS_FM_MM<bits<2> fmt> : MMArch { bits<5> fs; bits<5> ft; + bits<3> fcc; bits<4> cond; bits<32> Inst; @@ -773,13 +774,17 @@ class CEQS_FM_MM<bits<2> fmt> : MMArch { let Inst{31-26} = 0x15; let Inst{25-21} = ft; let Inst{20-16} = fs; - let Inst{15-13} = 0x0; // cc + let Inst{15-13} = fcc; let Inst{12} = 0; let Inst{11-10} = fmt; let Inst{9-6} = cond; let Inst{5-0} = 0x3c; } +class C_COND_FM_MM<bits <2> fmt, bits<4> c> : CEQS_FM_MM<fmt> { + let cond = c; +} + class BC1F_FM_MM<bits<5> tf> : MMArch { bits<16> offset; Modified: projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -1037,6 +1037,22 @@ void MipsAsmPrinter::PrintDebugValueComm // TODO: implement } +// Emit .dtprelword or .dtpreldword directive +// and value for debug thread local expression. +void MipsAsmPrinter::EmitDebugValue(const MCExpr *Value, + unsigned Size) const { + switch (Size) { + case 4: + OutStreamer->EmitDTPRel32Value(Value); + break; + case 8: + OutStreamer->EmitDTPRel64Value(Value); + break; + default: + llvm_unreachable("Unexpected size of expression value."); + } +} + // Align all targets of indirect branches on bundle size. Used only if target // is NaCl. void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) { Modified: projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.h ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.h Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.h Wed Feb 1 21:57:07 2017 (r313067) @@ -140,6 +140,7 @@ public: void EmitStartOfAsmFile(Module &M) override; void EmitEndOfAsmFile(Module &M) override; void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); + void EmitDebugValue(const MCExpr *Value, unsigned Size) const override; }; } Modified: projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -698,8 +698,8 @@ bool MipsFastISel::emitCmp(unsigned Resu unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass); emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); - emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( - Mips::FCC0, RegState::ImplicitDefine); + emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) + .addReg(RightReg); emitInst(CondMovOpc, ResultReg) .addReg(RegWithOne) .addReg(Mips::FCC0) Modified: projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td Wed Feb 1 21:57:07 2017 (r313067) @@ -219,6 +219,7 @@ class BC1F_FT<string opstr, DAGOperand o let isTerminator = 1; let hasDelaySlot = DelaySlot; let Defs = [AT]; + let hasFCCRegOperand = 1; } class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, @@ -229,41 +230,106 @@ class CEQS_FT<string typestr, RegisterCl !strconcat("c.$cond.", typestr)>, HARDFLOAT { let Defs = [FCC0]; let isCodeGenOnly = 1; + let hasFCCRegOperand = 1; } + +// Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather +// duplicating the instruction definition for MIPS1 - MIPS3, we expand +// c.cond.ft if necessary, and reject it after constructing the +// instruction if the ISA doesn't support it. class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, InstrItinClass itin> : - InstSE<(outs), (ins RC:$fs, RC:$ft), - !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin, - FrmFR>, HARDFLOAT; + InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft), + !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin, + FrmFR>, HARDFLOAT { + let isCompare = 1; + let hasFCCRegOperand = 1; +} + multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, InstrItinClass itin> { - def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>; - def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>; - def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>; - def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>; - def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>; - def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>; - def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>; - def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>; - def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>; - def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>; - def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>; - def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>; - def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>; - def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>; - def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>; - def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>; + def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, + C_COND_FM<fmt, 0> { + let BaseOpcode = "c.f."#NAME; + let isCommutable = 1; + } + def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, + C_COND_FM<fmt, 1> { + let BaseOpcode = "c.un."#NAME; + let isCommutable = 1; + } + def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, + C_COND_FM<fmt, 2> { + let BaseOpcode = "c.eq."#NAME; + let isCommutable = 1; + } + def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, + C_COND_FM<fmt, 3> { + let BaseOpcode = "c.ueq."#NAME; + let isCommutable = 1; + } + def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, + C_COND_FM<fmt, 4> { + let BaseOpcode = "c.olt."#NAME; + } + def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, + C_COND_FM<fmt, 5> { + let BaseOpcode = "c.ult."#NAME; + } + def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, + C_COND_FM<fmt, 6> { + let BaseOpcode = "c.ole."#NAME; + } + def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, + C_COND_FM<fmt, 7> { + let BaseOpcode = "c.ule."#NAME; + } + def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, + C_COND_FM<fmt, 8> { + let BaseOpcode = "c.sf."#NAME; + let isCommutable = 1; + } + def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, + C_COND_FM<fmt, 9> { + let BaseOpcode = "c.ngle."#NAME; + } + def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, + C_COND_FM<fmt, 10> { + let BaseOpcode = "c.seq."#NAME; + let isCommutable = 1; + } + def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, + C_COND_FM<fmt, 11> { + let BaseOpcode = "c.ngl."#NAME; + } + def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, + C_COND_FM<fmt, 12> { + let BaseOpcode = "c.lt."#NAME; + } + def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, + C_COND_FM<fmt, 13> { + let BaseOpcode = "c.nge."#NAME; + } + def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, + C_COND_FM<fmt, 14> { + let BaseOpcode = "c.le."#NAME; + } + def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, + C_COND_FM<fmt, 15> { + let BaseOpcode = "c.ngt."#NAME; + } } +let AdditionalPredicates = [NotInMicroMips] in { defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, FGR_32; let DecoderNamespace = "Mips64" in defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, FGR_64; - +} //===----------------------------------------------------------------------===// // Floating Point Instructions //===----------------------------------------------------------------------===// @@ -549,13 +615,29 @@ def BC1TL : MMRel, BC1F_FT<"bc1tl", brta /// Floating Point Compare let AdditionalPredicates = [NotInMicroMips] in { def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, - ISA_MIPS1_NOT_32R6_64R6; + ISA_MIPS1_NOT_32R6_64R6 { + + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; + } def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, - ISA_MIPS1_NOT_32R6_64R6, FGR_32; + ISA_MIPS1_NOT_32R6_64R6, FGR_32 { + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; + } } let DecoderNamespace = "Mips64" in def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, - ISA_MIPS1_NOT_32R6_64R6, FGR_64; + ISA_MIPS1_NOT_32R6_64R6, FGR_64 { + // FIXME: This is a required to work around the fact that thiese instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; +} //===----------------------------------------------------------------------===// // Floating Point Pseudo-Instructions @@ -602,15 +684,6 @@ def PseudoTRUNC_W_D : MipsAsmPseudoInst< //===----------------------------------------------------------------------===// // InstAliases. //===----------------------------------------------------------------------===// -def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>, - ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; -def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>, - ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT; -def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>, - ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; -def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>, - ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT; - def : MipsInstAlias <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, ISA_MIPS2, HARDFLOAT; @@ -630,6 +703,80 @@ def : MipsInstAlias def : MipsInstAlias <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, FGR_64, ISA_MIPS2, HARDFLOAT; + +multiclass C_COND_ALIASES<string TypeStr, RegisterOperand RC> { + def : MipsInstAlias<!strconcat("c.f.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_F_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.un.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_UN_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.eq.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_EQ_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ueq.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_UEQ_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.olt.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_OLT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ult.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_ULT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ole.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_OLE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ule.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_ULE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.sf.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_SF_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ngle.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_NGLE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.seq.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_SEQ_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ngl.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_NGL_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.lt.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_LT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.nge.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_NGE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.le.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_LE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ngt.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_NGT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; +} + +multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString, + Instruction BCFalse, string BCFalseString> { + def : MipsInstAlias<!strconcat(BCTrueString, " $offset"), + (BCTrue FCC0, brtarget:$offset), 1>; + + def : MipsInstAlias<!strconcat(BCFalseString, " $offset"), + (BCFalse FCC0, brtarget:$offset), 1>; +} + +let AdditionalPredicates = [NotInMicroMips] in { + defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6; + defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_32; + defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_64; + + defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6, + HARDFLOAT; + defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6, + HARDFLOAT; +} //===----------------------------------------------------------------------===// // Floating Point Patterns //===----------------------------------------------------------------------===// Modified: projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td Wed Feb 1 21:57:07 2017 (r313067) @@ -101,12 +101,15 @@ class MipsInst<dag outs, dag ins, string bit IsPCRelativeLoad = 0; // Load instruction with implicit source register // ($pc) and with explicit offset and destination // register + bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is + // present in MIPS-I to MIPS-III. - // TSFlags layout should be kept in sync with MipsInstrInfo.h. + // TSFlags layout should be kept in sync with MCTargetDesc/MipsBaseInfo.h. let TSFlags{3-0} = FormBits; let TSFlags{4} = isCTI; let TSFlags{5} = hasForbiddenSlot; let TSFlags{6} = IsPCRelativeLoad; + let TSFlags{7} = hasFCCRegOperand; let DecoderNamespace = "Mips"; @@ -829,6 +832,7 @@ class BC1F_FM<bit nd, bit tf> : StdArch class CEQS_FM<bits<5> fmt> : StdArch { bits<5> fs; bits<5> ft; + bits<3> fcc; bits<4> cond; bits<32> Inst; @@ -837,7 +841,7 @@ class CEQS_FM<bits<5> fmt> : StdArch { let Inst{25-21} = fmt; let Inst{20-16} = ft; let Inst{15-11} = fs; - let Inst{10-8} = 0; // cc + let Inst{10-8} = fcc; let Inst{7-4} = 0x3; let Inst{3-0} = cond; } Modified: projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -148,3 +148,11 @@ MCSection *MipsTargetObjectFile::getSect // Otherwise, we work the same as ELF. return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Align); } + +const MCExpr * +MipsTargetObjectFile::getDebugThreadLocalSymbol(const MCSymbol *Sym) const { + const MCExpr *Expr = + MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + return MCBinaryExpr::createAdd( + Expr, MCConstantExpr::create(0x8000, getContext()), getContext()); +} Modified: projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.h ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.h Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.h Wed Feb 1 21:57:07 2017 (r313067) @@ -42,6 +42,8 @@ class MipsTargetMachine; MCSection *getSectionForConstant(const DataLayout &DL, SectionKind Kind, const Constant *C, unsigned &Align) const override; + /// Describe a TLS variable address within debug info. + const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const override; }; } // end namespace llvm Modified: projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td Wed Feb 1 21:57:07 2017 (r313067) @@ -1508,8 +1508,14 @@ def DCBTST : DCB_Form_hint<246, (outs), PPC970_DGroup_Single; } // hasSideEffects = 0 +def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), + "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; +def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), + "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; +def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), + "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; def : Pat<(int_ppc_dcbt xoaddr:$dst), (DCBT 0, xoaddr:$dst)>; @@ -2381,6 +2387,13 @@ def MTSPR : XFXForm_1<31, 467, (outs), ( def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), "mftb $RT, $SPR", IIC_SprMFTB>; +def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), + "mfpmr $RT, $SPR", IIC_SprMFPMR>; + +def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), + "mtpmr $SPR, $RT", IIC_SprMTPMR>; + + // A pseudo-instruction used to implement the read of the 64-bit cycle counter // on a 32-bit target. let hasSideEffects = 1, usesCustomInserter = 1 in Modified: projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCSchedule.td ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCSchedule.td Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCSchedule.td Wed Feb 1 21:57:07 2017 (r313067) @@ -118,6 +118,8 @@ def IIC_SprTLBIE : InstrItinClass; def IIC_SprABORT : InstrItinClass; def IIC_SprMSGSYNC : InstrItinClass; def IIC_SprSTOP : InstrItinClass; +def IIC_SprMFPMR : InstrItinClass; +def IIC_SprMTPMR : InstrItinClass; //===----------------------------------------------------------------------===// // Processor instruction itineraries. Modified: projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td Wed Feb 1 21:57:07 2017 (r313067) @@ -249,6 +249,10 @@ def PPCE500mcItineraries : ProcessorItin InstrStage<5, [E500_SFX0]>], [8, 1], [E500_GPR_Bypass, E500_CR_Bypass]>, + InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<4, [E500_SFX0]>], + [7, 1], // Latency = 4, Repeat rate = 4 + [E500_GPR_Bypass, E500_GPR_Bypass]>, InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrStage<4, [E500_SFX0]>], [7, 1], // Latency = 4, Repeat rate = 4 @@ -257,6 +261,10 @@ def PPCE500mcItineraries : ProcessorItin InstrStage<1, [E500_SFX0, E500_SFX1]>], [4, 1], // Latency = 1, Repeat rate = 1 [E500_GPR_Bypass, E500_CR_Bypass]>, + InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0]>], + [4, 1], // Latency = 1, Repeat rate = 1 + [E500_CR_Bypass, E500_GPR_Bypass]>, InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrStage<4, [E500_SFX0]>], [7, 1], // Latency = 4, Repeat rate = 4 Modified: projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCScheduleE5500.td ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCScheduleE5500.td Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Target/PowerPC/PPCScheduleE5500.td Wed Feb 1 21:57:07 2017 (r313067) @@ -313,20 +313,24 @@ def PPCE5500Itineraries : ProcessorItine InstrStage<5, [E5500_CFX_0]>], [9, 2], // Latency = 5, Repeat rate = 5 [E5500_GPR_Bypass, E5500_CR_Bypass]>, - InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, - InstrStage<4, [E5500_SFX0]>], + InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<4, [E5500_CFX_0]>], [8, 2], // Latency = 4, Repeat rate = 4 [E5500_GPR_Bypass, E5500_GPR_Bypass]>, InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, InstrStage<1, [E5500_CFX_0]>], [5], // Latency = 1, Repeat rate = 1 [E5500_GPR_Bypass]>, + InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_CFX_0]>], + [5], // Latency = 1, Repeat rate = 1 + [E5500_GPR_Bypass]>, InstrItinData<IIC_SprMFTB, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, InstrStage<4, [E5500_CFX_0]>], [8, 2], // Latency = 4, Repeat rate = 4 [NoBypass, E5500_GPR_Bypass]>, InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, - InstrStage<1, [E5500_SFX0, E5500_SFX1]>], + InstrStage<1, [E5500_CFX_0]>], [5], // Latency = 1, Repeat rate = 1 [E5500_GPR_Bypass]>, InstrItinData<IIC_FPGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, Modified: projects/clang400-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -884,6 +884,10 @@ static Instruction *transformToIndexedCo if (!GEPLHS->hasAllConstantIndices()) return nullptr; + // Make sure the pointers have the same type. + if (GEPLHS->getType() != RHS->getType()) + return nullptr; + Value *PtrBase, *Index; std::tie(PtrBase, Index) = getAsConstantIndexedAddress(GEPLHS, DL); Modified: projects/clang400-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -502,7 +502,8 @@ static Instruction *combineLoadToOperati !DL.isNonIntegralPointerType(Ty)) { if (all_of(LI.users(), [&LI](User *U) { auto *SI = dyn_cast<StoreInst>(U); - return SI && SI->getPointerOperand() != &LI; + return SI && SI->getPointerOperand() != &LI && + !SI->getPointerOperand()->isSwiftError(); })) { LoadInst *NewLoad = combineLoadToNewType( IC, LI, Modified: projects/clang400-import/contrib/llvm/lib/Transforms/Scalar/SCCP.cpp ============================================================================== --- projects/clang400-import/contrib/llvm/lib/Transforms/Scalar/SCCP.cpp Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/lib/Transforms/Scalar/SCCP.cpp Wed Feb 1 21:57:07 2017 (r313067) @@ -1705,7 +1705,10 @@ static bool runIPSCCP(Module &M, const D // If this is an exact definition of this function, then we can propagate // information about its result into callsites of it. - if (F.hasExactDefinition()) + // Don't touch naked functions. They may contain asm returning a + // value we don't see, so we may end up interprocedurally propagating + // the return value incorrectly. + if (F.hasExactDefinition() && !F.hasFnAttribute(Attribute::Naked)) Solver.AddTrackedFunction(&F); // If this function only has direct calls that we can see, we can track its Modified: projects/clang400-import/contrib/llvm/tools/clang/include/clang/AST/Type.h ============================================================================== --- projects/clang400-import/contrib/llvm/tools/clang/include/clang/AST/Type.h Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/tools/clang/include/clang/AST/Type.h Wed Feb 1 21:57:07 2017 (r313067) @@ -3827,13 +3827,13 @@ private: friend class ASTContext; // creates these - AttributedType(QualType canon, Kind attrKind, - QualType modified, QualType equivalent) - : Type(Attributed, canon, canon->isDependentType(), - canon->isInstantiationDependentType(), - canon->isVariablyModifiedType(), - canon->containsUnexpandedParameterPack()), - ModifiedType(modified), EquivalentType(equivalent) { + AttributedType(QualType canon, Kind attrKind, QualType modified, + QualType equivalent) + : Type(Attributed, canon, equivalent->isDependentType(), + equivalent->isInstantiationDependentType(), + equivalent->isVariablyModifiedType(), + equivalent->containsUnexpandedParameterPack()), + ModifiedType(modified), EquivalentType(equivalent) { AttributedTypeBits.AttrKind = attrKind; } Modified: projects/clang400-import/contrib/llvm/tools/clang/include/clang/Basic/DiagnosticSemaKinds.td ============================================================================== --- projects/clang400-import/contrib/llvm/tools/clang/include/clang/Basic/DiagnosticSemaKinds.td Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/tools/clang/include/clang/Basic/DiagnosticSemaKinds.td Wed Feb 1 21:57:07 2017 (r313067) @@ -3373,7 +3373,8 @@ def note_ovl_candidate_has_pass_object_s "candidate address cannot be taken because parameter %0 has " "pass_object_size attribute">; def err_diagnose_if_succeeded : Error<"%0">; -def warn_diagnose_if_succeeded : Warning<"%0">, InGroup<UserDefinedWarnings>; +def warn_diagnose_if_succeeded : Warning<"%0">, InGroup<UserDefinedWarnings>, + ShowInSystemHeader; def note_ovl_candidate_disabled_by_function_cond_attr : Note< "candidate disabled: %0">; def note_ovl_candidate_disabled_by_extension : Note< Modified: projects/clang400-import/contrib/llvm/tools/clang/include/clang/Sema/Overload.h ============================================================================== --- projects/clang400-import/contrib/llvm/tools/clang/include/clang/Sema/Overload.h Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/tools/clang/include/clang/Sema/Overload.h Wed Feb 1 21:57:07 2017 (r313067) @@ -675,26 +675,6 @@ namespace clang { /// to be used while performing partial ordering of function templates. unsigned ExplicitCallArguments; - /// The number of diagnose_if attributes that this overload triggered. - /// If any of the triggered attributes are errors, this won't count - /// diagnose_if warnings. - unsigned NumTriggeredDiagnoseIfs = 0; - - /// Basically a TinyPtrVector<DiagnoseIfAttr *> that doesn't own the vector: - /// If NumTriggeredDiagnoseIfs is 0 or 1, this is a DiagnoseIfAttr *, - /// otherwise it's a pointer to an array of `NumTriggeredDiagnoseIfs` - /// DiagnoseIfAttr *s. - llvm::PointerUnion<DiagnoseIfAttr *, DiagnoseIfAttr **> DiagnoseIfInfo; - - /// Gets an ArrayRef for the data at DiagnoseIfInfo. Note that this may give - /// you a pointer into DiagnoseIfInfo. - ArrayRef<DiagnoseIfAttr *> getDiagnoseIfInfo() const { - auto *Ptr = NumTriggeredDiagnoseIfs <= 1 - ? DiagnoseIfInfo.getAddrOfPtr1() - : DiagnoseIfInfo.get<DiagnoseIfAttr **>(); - return {Ptr, NumTriggeredDiagnoseIfs}; - } - union { DeductionFailureInfo DeductionFailure; @@ -759,9 +739,8 @@ namespace clang { SmallVector<OverloadCandidate, 16> Candidates; llvm::SmallPtrSet<Decl *, 16> Functions; - // Allocator for ConversionSequenceLists and DiagnoseIfAttr* arrays. - // We store the first few of each of these inline to avoid allocation for - // small sets. + // Allocator for ConversionSequenceLists. We store the first few of these + // inline to avoid allocation for small sets. llvm::BumpPtrAllocator SlabAllocator; SourceLocation Loc; @@ -776,6 +755,8 @@ namespace clang { /// from the slab allocator. /// FIXME: It would probably be nice to have a SmallBumpPtrAllocator /// instead. + /// FIXME: Now that this only allocates ImplicitConversionSequences, do we + /// want to un-generalize this? template <typename T> T *slabAllocate(unsigned N) { // It's simpler if this doesn't need to consider alignment. @@ -809,11 +790,6 @@ namespace clang { SourceLocation getLocation() const { return Loc; } CandidateSetKind getKind() const { return Kind; } - /// Make a DiagnoseIfAttr* array in a block of memory that will live for - /// as long as this OverloadCandidateSet. Returns a pointer to the start - /// of that array. - DiagnoseIfAttr **addDiagnoseIfComplaints(ArrayRef<DiagnoseIfAttr *> CA); - /// \brief Determine when this overload candidate will be new to the /// overload set. bool isNewCandidate(Decl *F) { Modified: projects/clang400-import/contrib/llvm/tools/clang/include/clang/Sema/Sema.h ============================================================================== --- projects/clang400-import/contrib/llvm/tools/clang/include/clang/Sema/Sema.h Wed Feb 1 21:44:50 2017 (r313066) +++ projects/clang400-import/contrib/llvm/tools/clang/include/clang/Sema/Sema.h Wed Feb 1 21:57:07 2017 (r313067) @@ -2532,14 +2532,14 @@ public: void AddMethodCandidate(DeclAccessPair FoundDecl, QualType ObjectType, Expr::Classification ObjectClassification, - Expr *ThisArg, ArrayRef<Expr *> Args, + ArrayRef<Expr *> Args, OverloadCandidateSet& CandidateSet, bool SuppressUserConversion = false); void AddMethodCandidate(CXXMethodDecl *Method, DeclAccessPair FoundDecl, CXXRecordDecl *ActingContext, QualType ObjectType, Expr::Classification ObjectClassification, - Expr *ThisArg, ArrayRef<Expr *> Args, + ArrayRef<Expr *> Args, OverloadCandidateSet& CandidateSet, bool SuppressUserConversions = false, bool PartialOverloading = false, @@ -2550,7 +2550,6 @@ public: TemplateArgumentListInfo *ExplicitTemplateArgs, QualType ObjectType, Expr::Classification ObjectClassification, - Expr *ThisArg, ArrayRef<Expr *> Args, OverloadCandidateSet& CandidateSet, bool SuppressUserConversions = false, @@ -2624,37 +2623,27 @@ public: *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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