Date: Sun, 03 May 2015 20:11:11 +0000 From: bugzilla-noreply@freebsd.org To: freebsd-arm@FreeBSD.org Subject: [Bug 199740] syscall __clear_cache (ARM_SYNC_ICACHE) does not achieve icache consistency Message-ID: <bug-199740-7-jTvb6bsWfS@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-199740-7@https.bugs.freebsd.org/bugzilla/> References: <bug-199740-7@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=199740 Ian Lepore <ian@FreeBSD.org> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |ian@FreeBSD.org --- Comment #1 from Ian Lepore <ian@FreeBSD.org> --- The ARM ARM, in a rare example of lucidity, describes the register parameter for cp15 cache operations thusly: "When the data is stated to be an MVA, it does not have to be cache line aligned. If these changes lead to something working that doesn't work without the changes, I guess we need to figure out why. It may imply that the caller to the function is incorrectly converting a start/end tulple to start/len or something along those lines. -- You are receiving this mail because: You are the assignee for the bug.
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