Date: Fri, 5 Feb 2021 14:04:39 GMT From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 13ec5a6da04b - main - Add support for arm64 nGnRE device memory Message-ID: <202102051404.115E4d1W028010@gitrepo.freebsd.org>
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The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=13ec5a6da04b14c4d40d3b37335dfaef7469aeb5 commit 13ec5a6da04b14c4d40d3b37335dfaef7469aeb5 Author: Andrew Turner <andrew@FreeBSD.org> AuthorDate: 2021-02-05 10:50:29 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2021-02-05 12:25:56 +0000 Add support for arm64 nGnRE device memory On arm64 we can select how strongly we order device memory. Currently we use the strongest type of non-Gathering, non-Reordering, no Early write acknowledgement. This is equivalent to VM_MEMATTR_SO in the 32-bit arm code. Create a new memory type to remove the no Early write acknowledgement option to create a memory attribute that is equivalent to the arm VM_MEMATTR_DEVICE. Keep the the old nGnRnE memory as what we provide for VM_MEMATTR_DEVICE until we can test nGnRE on more hardware. A method for dynamically switching back may be needed as at least one vendor is known to have broken nGnRE memory. Sponsored by: Innovate UK --- sys/arm64/arm64/locore.S | 5 +++-- sys/arm64/include/armreg.h | 1 + sys/arm64/include/vm.h | 5 ++++- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S index c62a2a5bd626..b340041eb163 100644 --- a/sys/arm64/arm64/locore.S +++ b/sys/arm64/arm64/locore.S @@ -733,10 +733,11 @@ LENTRY(start_mmu) .align 3 mair: - .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE) | \ + .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \ MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \ MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \ - MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) + MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \ + MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE) tcr: .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | \ TCR_CACHE_ATTRS | TCR_SMP_ATTRS) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 201d7559320b..f5d25a572466 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -734,6 +734,7 @@ #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) #define MAIR_DEVICE_nGnRnE 0x00 +#define MAIR_DEVICE_nGnRE 0x04 #define MAIR_NORMAL_NC 0x44 #define MAIR_NORMAL_WT 0xbb #define MAIR_NORMAL_WB 0xff diff --git a/sys/arm64/include/vm.h b/sys/arm64/include/vm.h index dac13980060e..3df3af24c010 100644 --- a/sys/arm64/include/vm.h +++ b/sys/arm64/include/vm.h @@ -30,10 +30,13 @@ #define _MACHINE_VM_H_ /* Memory attribute configuration. */ -#define VM_MEMATTR_DEVICE 0 +#define VM_MEMATTR_DEVICE_nGnRnE 0 #define VM_MEMATTR_UNCACHEABLE 1 #define VM_MEMATTR_WRITE_BACK 2 #define VM_MEMATTR_WRITE_THROUGH 3 +#define VM_MEMATTR_DEVICE_nGnRE 4 + +#define VM_MEMATTR_DEVICE VM_MEMATTR_DEVICE_nGnRnE #ifdef _KERNEL /* If defined vmstat will try to use both of these in a switch statement */
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