Date: Sat, 30 Apr 2005 19:39:28 +0000 (UTC) From: Doug White <dwhite@FreeBSD.org> To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org Subject: cvs commit: src/sys/amd64/amd64 mp_machdep.c src/sys/i386/i386 mp_machdep.c Message-ID: <200504301939.j3UJdSD4085056@repoman.freebsd.org>
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dwhite 2005-04-30 19:39:28 UTC
FreeBSD src repository
Modified files: (Branch: RELENG_5)
sys/amd64/amd64 mp_machdep.c
sys/i386/i386 mp_machdep.c
Log:
Enable interrupts in smp_tlb_shootdown() and smp_targeted_tlb_shootdown()
to workaround Opteron Errata 106. The while loop runs entirely out of
the instruction cache, which blocks updates to the cache from other CPUs.
Interrupts break the lock, allowing the write to post.
Many thanks to Paul Vixie and Peter Losher at ISC for providing resources
to troubleshoot the issue; Stephen Uphoff and Alan Cox for their
expertise; and the rest of the RE team for pushing the resolution along
so we can ship 5.4 with this fix.
Revision Changes Path
1.242.2.9 +16 -0 src/sys/amd64/amd64/mp_machdep.c
1.235.2.8 +16 -0 src/sys/i386/i386/mp_machdep.c
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