Date: Mon, 25 Jul 2011 14:45:13 +0000 (UTC) From: Marius Strobl <marius@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-7@freebsd.org Subject: svn commit: r224316 - in stable/7/sys/sparc64: include sbus sparc64 Message-ID: <201107251445.p6PEjDC4060993@svn.freebsd.org>
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Author: marius Date: Mon Jul 25 14:45:13 2011 New Revision: 224316 URL: http://svn.freebsd.org/changeset/base/224316 Log: MFC: r220939 Correct spelling in comments. Submitted by: brucec Modified: stable/7/sys/sparc64/include/cpufunc.h stable/7/sys/sparc64/sbus/lsi64854.c stable/7/sys/sparc64/sbus/ofw_sbus.h stable/7/sys/sparc64/sparc64/exception.S stable/7/sys/sparc64/sparc64/machdep.c stable/7/sys/sparc64/sparc64/pmap.c Directory Properties: stable/7/sys/ (props changed) stable/7/sys/cddl/contrib/opensolaris/ (props changed) stable/7/sys/contrib/dev/acpica/ (props changed) stable/7/sys/contrib/pf/ (props changed) Modified: stable/7/sys/sparc64/include/cpufunc.h ============================================================================== --- stable/7/sys/sparc64/include/cpufunc.h Mon Jul 25 14:44:00 2011 (r224315) +++ stable/7/sys/sparc64/include/cpufunc.h Mon Jul 25 14:45:13 2011 (r224316) @@ -187,7 +187,7 @@ int fasword32(u_long asi, void *addr, ui /* * Macro intended to be used instead of wr(asr23, val, xorval) for writing to * the TICK_COMPARE register in order to avoid a bug in BlackBird CPUs that - * can cause these writes to fail under certain condidtions which in turn + * can cause these writes to fail under certain conditions which in turn * causes the hardclock to stop. The workaround is to read the TICK_COMPARE * register back immediately after writing to it with these two instructions * aligned to a quadword boundary in order to ensure that I$ misses won't Modified: stable/7/sys/sparc64/sbus/lsi64854.c ============================================================================== --- stable/7/sys/sparc64/sbus/lsi64854.c Mon Jul 25 14:44:00 2011 (r224315) +++ stable/7/sys/sparc64/sbus/lsi64854.c Mon Jul 25 14:45:13 2011 (r224316) @@ -528,7 +528,7 @@ lsi64854_scsi_intr(void *arg) } trans = sc->sc_dmasize - resid; - if (trans < 0) { /* transfered < 0? */ + if (trans < 0) { /* transferred < 0? */ #if 0 /* * This situation can happen in perfectly normal operation @@ -718,7 +718,7 @@ lsi64854_pp_intr(void *arg) sc->sc_active = 0; trans = sc->sc_dmasize - resid; - if (trans < 0) /* transfered < 0? */ + if (trans < 0) /* transferred < 0? */ trans = sc->sc_dmasize; *sc->sc_dmalen -= trans; *sc->sc_dmaaddr += trans; Modified: stable/7/sys/sparc64/sbus/ofw_sbus.h ============================================================================== --- stable/7/sys/sparc64/sbus/ofw_sbus.h Mon Jul 25 14:44:00 2011 (r224315) +++ stable/7/sys/sparc64/sbus/ofw_sbus.h Mon Jul 25 14:45:13 2011 (r224316) @@ -41,7 +41,7 @@ struct sbus_regs { u_int32_t sbr_size; }; -/* Address translation accross busses */ +/* Address translation across busses */ struct sbus_ranges { u_int32_t cspace; /* Client space */ u_int32_t coffset; /* Client offset */ Modified: stable/7/sys/sparc64/sparc64/exception.S ============================================================================== --- stable/7/sys/sparc64/sparc64/exception.S Mon Jul 25 14:44:00 2011 (r224315) +++ stable/7/sys/sparc64/sparc64/exception.S Mon Jul 25 14:45:13 2011 (r224316) @@ -377,7 +377,7 @@ END(rsf_fatal) * Due to its size a trap table is an inherently hard thing to represent in * code in a clean way. There are approximately 1024 vectors, of 8 or 32 * instructions each, many of which are identical. The way that this is - * layed out is the instructions (8 or 32) for the actual trap vector appear + * laid out is the instructions (8 or 32) for the actual trap vector appear * as an AS macro. In general this code branches to tl0_trap or tl1_trap, * but if not supporting code can be placed just after the definition of the * macro. The macros are then instantiated in a different section (.trap), @@ -2405,7 +2405,7 @@ ENTRY(tl0_ret) * Check for pending asts atomically with returning. We must raise * the PIL before checking, and if no asts are found the PIL must * remain raised until the retry is executed, or we risk missing asts - * caused by interrupts occuring after the test. If the PIL is + * caused by interrupts occurring after the test. If the PIL is * lowered, as it is when we call ast, the check must be re-executed. */ wrpr %g0, PIL_TICK, %pil Modified: stable/7/sys/sparc64/sparc64/machdep.c ============================================================================== --- stable/7/sys/sparc64/sparc64/machdep.c Mon Jul 25 14:44:00 2011 (r224315) +++ stable/7/sys/sparc64/sparc64/machdep.c Mon Jul 25 14:45:13 2011 (r224316) @@ -557,7 +557,7 @@ sparc64_init(caddr_t mdp, u_long o1, u_l * is necessary in order to set obp-control-relinquished to true * within the PROM so obtaining /virtual-memory/translations doesn't * trigger a fatal reset error or worse things further down the road. - * XXX it should be possible to use this soley instead of writing + * XXX it should be possible to use this solely instead of writing * %tba in cpu_setregs(). Doing so causes a hang however. */ sun4u_set_traptable(tl0_base); Modified: stable/7/sys/sparc64/sparc64/pmap.c ============================================================================== --- stable/7/sys/sparc64/sparc64/pmap.c Mon Jul 25 14:44:00 2011 (r224315) +++ stable/7/sys/sparc64/sparc64/pmap.c Mon Jul 25 14:45:13 2011 (r224316) @@ -930,7 +930,7 @@ pmap_kenter(vm_offset_t va, vm_page_t m) /* * Map a wired page into kernel virtual address space. This additionally - * takes a flag argument wich is or'ed to the TTE data. This is used by + * takes a flag argument which is or'ed to the TTE data. This is used by * sparc64_bus_mem_map(). * NOTE: if the mapping is non-cacheable, it's the caller's responsibility * to flush entries that might still be in the cache, if applicable.
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