Date: Thu, 13 Sep 2018 09:26:16 +0000 (UTC) From: Marius Strobl <marius@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r338636 - stable/10/sys/dev/sdhci Message-ID: <201809130926.w8D9QGjg094638@repo.freebsd.org>
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Author: marius Date: Thu Sep 13 09:26:16 2018 New Revision: 338636 URL: https://svnweb.freebsd.org/changeset/base/338636 Log: MFC: r333613 The broken DDR52 support of Intel Bay Trail eMMC controllers rumored in the commit log of r321385 has been confirmed via the public VLI54 erratum. Thus, stop advertising DDR52 for these controllers. Note that this change should hardly make a difference in practice as eMMC chips from the same era as these SoCs most likely support HS200 at least, probably even up to HS400ES. Modified: stable/10/sys/dev/sdhci/sdhci_acpi.c stable/10/sys/dev/sdhci/sdhci_pci.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/dev/sdhci/sdhci_acpi.c ============================================================================== --- stable/10/sys/dev/sdhci/sdhci_acpi.c Thu Sep 13 09:20:13 2018 (r338635) +++ stable/10/sys/dev/sdhci/sdhci_acpi.c Thu Sep 13 09:26:16 2018 (r338636) @@ -60,7 +60,6 @@ static const struct sdhci_acpi_device { { "80860F14", 1, "Intel Bay Trail/Braswell eMMC 4.5/4.5.1 Controller", SDHCI_QUIRK_INTEL_POWER_UP_RESET | SDHCI_QUIRK_WAIT_WHILE_BUSY | - SDHCI_QUIRK_MMC_DDR52 | SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | SDHCI_QUIRK_PRESET_VALUE_BROKEN }, { "80860F14", 3, "Intel Bay Trail/Braswell SDXC Controller", @@ -261,11 +260,16 @@ sdhci_acpi_attach(device_t dev) return (ENOMEM); } - /* Intel Braswell eMMC 4.5.1 controller quirk */ + /* + * Intel Bay Trail and Braswell eMMC controllers share the same IDs, + * but while with these former DDR52 is affected by the VLI54 erratum, + * these latter require the timeout clock to be hardcoded to 1 MHz. + */ if (strcmp(acpi_dev->hid, "80860F14") == 0 && acpi_dev->uid == 1 && SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES) == 0x446cc8b2 && SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES2) == 0x00000807) - sc->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_1MHZ; + sc->quirks |= SDHCI_QUIRK_MMC_DDR52 | + SDHCI_QUIRK_DATA_TIMEOUT_1MHZ; sc->quirks &= ~sdhci_quirk_clear; sc->quirks |= sdhci_quirk_set; sc->slot.quirks = sc->quirks; Modified: stable/10/sys/dev/sdhci/sdhci_pci.c ============================================================================== --- stable/10/sys/dev/sdhci/sdhci_pci.c Thu Sep 13 09:20:13 2018 (r338635) +++ stable/10/sys/dev/sdhci/sdhci_pci.c Thu Sep 13 09:26:16 2018 (r338636) @@ -104,18 +104,18 @@ static const struct sdhci_device { { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", + /* DDR52 is supported but affected by the VLI54 erratum */ SDHCI_QUIRK_INTEL_POWER_UP_RESET | SDHCI_QUIRK_WAIT_WHILE_BUSY | - SDHCI_QUIRK_MMC_DDR52 | SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | SDHCI_QUIRK_PRESET_VALUE_BROKEN}, { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", SDHCI_QUIRK_WAIT_WHILE_BUSY | SDHCI_QUIRK_PRESET_VALUE_BROKEN }, { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", + /* DDR52 is supported but affected by the VLI54 erratum */ SDHCI_QUIRK_INTEL_POWER_UP_RESET | SDHCI_QUIRK_WAIT_WHILE_BUSY | - SDHCI_QUIRK_MMC_DDR52 | SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | SDHCI_QUIRK_PRESET_VALUE_BROKEN }, { 0x19db8086, 0xffff, "Intel Denverton eMMC 5.0 Controller",
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