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Date:      Sun, 11 Jun 1995 19:58:45 +0200
From:      esser@zpr.uni-koeln.de (Stefan Esser)
To:        John Herks <john@pyromania.apana.org.au>
Cc:        hackers@freebsd.org
Subject:   Re: Intel Triton chipset & 2.0R
Message-ID:  <199506111758.AA12392@FileServ1.MI.Uni-Koeln.DE>

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On Jun 9, 19:08, Terry Lambert wrote:
} Subject: Re: Intel Triton chipset & 2.0R
} > I have just upgraded from a Neptune based Pentium motherboard to a Triton 
} > chipset motherboard.
} > 
} > Before on the pci bus scan I used to get -:
} > 
} > 8243LX - pci cache controller
} > 82378LB - pci isa bridge
} > 
} > Now I get the following output -:
} >
} > pci0: scanning device 0..31, mechanism=1.
} > pci0:0: INTEL CORPORATION, device=0x122d, class=bridge [not supported]
} >                                           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
} > 
} > pci0:7: INTEL CORPORATION, device=0x122e, class=bridge [not supported]
} >                                           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Well, yes, this [not supported] message is misleading ...

It doesn't mean that the Triton doesn't work, but it just
says that there is no special PCI device driver for it.

And none is required, actually ...
The BIOS does all the initialisation, and FreeBSD's best
guess is that the BIOS did it right ...

What happens after these messages ?

I've heard that Triton based system run just fine with 
FreeBSD-current, so I'd like to hear about the exact 
failure mode (if any) ...

} > pci uses physical addresses from 0xc0000000 to 0xc0001000

Seems that 4KB of RAM are assigned to memory mapped PCI
devices. Seems to work fine so far ...

} PCI 1.x vs. 2.0 and fallback.
} 
} Will probably be fixed when the Compaq Proliany fix goes in.

I'm working on this. The problem with a fix is, that the PCI
specs explicitly expect the configuration space enable register 
to ignore byte accesses if mechanism 1 is used.
I'll have to send patches that check for this feature ...

} Don't worry about it if it can run in a fallback mode.  The Compaq
} apparently needs manual fallback to make it run, so they're actually
} much worse off than you are.

I'll test a few methods to distingiush mechanism 1 and 2
compliant CPU to PCI bridge devices, and hope this problem 
is fixed tomorrow. 

Too bad it can't go into 2.0.5 anymore ...


STefan



-- 
 Stefan Esser				Internet:	<se@ZPR.Uni-Koeln.DE>
 Zentrum fuer Paralleles Rechnen	Tel:		+49 221 4706017
 Universitaet zu Koeln			FAX:		+49 221 4705160
 Weyertal 80
 50931 Koeln



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