Date: Sat, 20 Feb 2010 17:19:17 +0000 (UTC) From: Randall Stewart <rrs@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r204136 - head/sys/mips/rmi Message-ID: <201002201719.o1KHJHt3068093@svn.freebsd.org>
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Author: rrs Date: Sat Feb 20 17:19:16 2010 New Revision: 204136 URL: http://svn.freebsd.org/changeset/base/204136 Log: Changes for pci and pci-e support - add bus_space_rmi_pci.c for PCI bus space - files.xlr update for changes in files - pcibus.c merged into xlr_pci.c (they were small files with inter-dependencies) - xlr_pci.c - lot of changes here with few fixes, formatting cleanup Obtained from: C. Jayachandran (JC) - c.jayachandran@gmail.com Modified: head/sys/mips/rmi/bus_space_rmi_pci.c head/sys/mips/rmi/files.xlr head/sys/mips/rmi/pcibus.h head/sys/mips/rmi/xlr_pci.c Modified: head/sys/mips/rmi/bus_space_rmi_pci.c ============================================================================== --- head/sys/mips/rmi/bus_space_rmi_pci.c Sat Feb 20 17:12:07 2010 (r204135) +++ head/sys/mips/rmi/bus_space_rmi_pci.c Sat Feb 20 17:19:16 2010 (r204136) @@ -23,6 +23,767 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * + * $FreeBSD$ + */ +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/endian.h> +#include <sys/malloc.h> +#include <sys/ktr.h> + +#include <vm/vm.h> +#include <vm/pmap.h> +#include <vm/vm_kern.h> +#include <vm/vm_extern.h> + +#include <machine/bus.h> +#include <machine/cache.h> + +static int +rmi_pci_bus_space_map(void *t, bus_addr_t addr, + bus_size_t size, int flags, + bus_space_handle_t * bshp); + +static void +rmi_pci_bus_space_unmap(void *t, bus_space_handle_t bsh, + bus_size_t size); + +static int +rmi_pci_bus_space_subregion(void *t, + bus_space_handle_t bsh, + bus_size_t offset, bus_size_t size, + bus_space_handle_t * nbshp); + +static u_int8_t +rmi_pci_bus_space_read_1(void *t, + bus_space_handle_t handle, + bus_size_t offset); + +static u_int16_t +rmi_pci_bus_space_read_2(void *t, + bus_space_handle_t handle, + bus_size_t offset); + +static u_int32_t +rmi_pci_bus_space_read_4(void *t, + bus_space_handle_t handle, + bus_size_t offset); + +static void +rmi_pci_bus_space_read_multi_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_region_1(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_region_4(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int32_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int8_t value); + +static void +rmi_pci_bus_space_write_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int16_t value); + +static void +rmi_pci_bus_space_write_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int32_t value); + +static void +rmi_pci_bus_space_write_multi_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_multi_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_multi_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int32_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_region_4(void *t, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int32_t * addr, + size_t count); + + +static void +rmi_pci_bus_space_set_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value, + size_t count); +static void +rmi_pci_bus_space_set_region_4(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int32_t value, + size_t count); + +static void +rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, + bus_size_t offset __unused, bus_size_t len __unused, int flags); + +static void +rmi_pci_bus_space_copy_region_2(void *t, + bus_space_handle_t bsh1, + bus_size_t off1, + bus_space_handle_t bsh2, + bus_size_t off2, size_t count); + +u_int8_t +rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle, + bus_size_t offset); + +static u_int16_t +rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset); + +static u_int32_t +rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset); +static void +rmi_pci_bus_space_read_multi_stream_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_stream_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_stream_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, + size_t count); + +void +rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t value); +static void +rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int16_t value); + +static void +rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int32_t value); + +static void +rmi_pci_bus_space_write_multi_stream_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int8_t * addr, + size_t count); +static void +rmi_pci_bus_space_write_multi_stream_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_multi_stream_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int32_t * addr, + size_t count); + +#define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__) + +static struct bus_space local_rmi_pci_bus_space = { + /* cookie */ + (void *)0, + + /* mapping/unmapping */ + rmi_pci_bus_space_map, + rmi_pci_bus_space_unmap, + rmi_pci_bus_space_subregion, + + /* allocation/deallocation */ + NULL, + NULL, + + /* barrier */ + rmi_pci_bus_space_barrier, + + /* read (single) */ + rmi_pci_bus_space_read_1, + rmi_pci_bus_space_read_2, + rmi_pci_bus_space_read_4, + NULL, + + /* read multiple */ + rmi_pci_bus_space_read_multi_1, + rmi_pci_bus_space_read_multi_2, + rmi_pci_bus_space_read_multi_4, + NULL, + + /* read region */ + rmi_pci_bus_space_read_region_1, + rmi_pci_bus_space_read_region_2, + rmi_pci_bus_space_read_region_4, + NULL, + + /* write (single) */ + rmi_pci_bus_space_write_1, + rmi_pci_bus_space_write_2, + rmi_pci_bus_space_write_4, + NULL, + + /* write multiple */ + rmi_pci_bus_space_write_multi_1, + rmi_pci_bus_space_write_multi_2, + rmi_pci_bus_space_write_multi_4, + NULL, + + /* write region */ + NULL, + rmi_pci_bus_space_write_region_2, + rmi_pci_bus_space_write_region_4, + NULL, + + /* set multiple */ + NULL, + NULL, + NULL, + NULL, + + /* set region */ + NULL, + rmi_pci_bus_space_set_region_2, + rmi_pci_bus_space_set_region_4, + NULL, + + /* copy */ + NULL, + rmi_pci_bus_space_copy_region_2, + NULL, + NULL, + + /* read (single) stream */ + rmi_pci_bus_space_read_stream_1, + rmi_pci_bus_space_read_stream_2, + rmi_pci_bus_space_read_stream_4, + NULL, + + /* read multiple stream */ + rmi_pci_bus_space_read_multi_stream_1, + rmi_pci_bus_space_read_multi_stream_2, + rmi_pci_bus_space_read_multi_stream_4, + NULL, + + /* read region stream */ + rmi_pci_bus_space_read_region_1, + rmi_pci_bus_space_read_region_2, + rmi_pci_bus_space_read_region_4, + NULL, + + /* write (single) stream */ + rmi_pci_bus_space_write_stream_1, + rmi_pci_bus_space_write_stream_2, + rmi_pci_bus_space_write_stream_4, + NULL, + + /* write multiple stream */ + rmi_pci_bus_space_write_multi_stream_1, + rmi_pci_bus_space_write_multi_stream_2, + rmi_pci_bus_space_write_multi_stream_4, + NULL, + + /* write region stream */ + NULL, + rmi_pci_bus_space_write_region_2, + rmi_pci_bus_space_write_region_4, + NULL, +}; + +/* generic bus_space tag */ +bus_space_tag_t rmi_pci_bus_space = &local_rmi_pci_bus_space; + +/* + * Map a region of device bus space into CPU virtual address space. + */ +static int +rmi_pci_bus_space_map(void *t __unused, bus_addr_t addr, + bus_size_t size __unused, int flags __unused, + bus_space_handle_t * bshp) +{ + *bshp = addr; + return (0); +} + +/* + * Unmap a region of device bus space. + */ +static void +rmi_pci_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused, + bus_size_t size __unused) +{ +} + +/* + * Get a new handle for a subregion of an already-mapped area of bus space. + */ + +static int +rmi_pci_bus_space_subregion(void *t __unused, bus_space_handle_t bsh, + bus_size_t offset, bus_size_t size __unused, + bus_space_handle_t * nbshp) +{ + *nbshp = bsh + offset; + return (0); +} + +/* + * Read a 1, 2, 4, or 8 byte quantity from bus space + * described by tag/handle/offset. + */ + +static u_int8_t +rmi_pci_bus_space_read_1(void *tag, bus_space_handle_t handle, + bus_size_t offset) +{ + return (u_int8_t) (*(volatile u_int8_t *)(handle + offset)); +} + +static u_int16_t +rmi_pci_bus_space_read_2(void *tag, bus_space_handle_t handle, + bus_size_t offset) +{ + return bswap16((u_int16_t) (*(volatile u_int16_t *)(handle + offset))); +} + +static u_int32_t +rmi_pci_bus_space_read_4(void *tag, bus_space_handle_t handle, + bus_size_t offset) +{ + return bswap32((*(volatile u_int32_t *)(handle + offset))); +} + + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle/offset and copy into buffer provided. + */ +static void +rmi_pci_bus_space_read_multi_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, size_t count) +{ + while (count--) { + *addr = (*(volatile u_int8_t *)(handle + offset)); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, size_t count) +{ + + while (count--) { + *addr = *(volatile u_int16_t *)(handle + offset); + *addr = bswap16(*addr); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, size_t count) +{ + + while (count--) { + *addr = *(volatile u_int32_t *)(handle + offset); + *addr = bswap32(*addr); + addr++; + } +} + +/* + * Write the 1, 2, 4, or 8 byte value `value' to bus space + * described by tag/handle/offset. + */ + +static void +rmi_pci_bus_space_write_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int8_t value) +{ + mips_sync(); + *(volatile u_int8_t *)(handle + offset) = value; +} + +static void +rmi_pci_bus_space_write_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int16_t value) +{ + mips_sync(); + *(volatile u_int16_t *)(handle + offset) = bswap16(value); +} + + +static void +rmi_pci_bus_space_write_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int32_t value) +{ + mips_sync(); + *(volatile u_int32_t *)(handle + offset) = bswap32(value); +} + +/* + * Write `count' 1, 2, 4, or 8 byte quantities from the buffer + * provided to bus space described by tag/handle/offset. + */ + + +static void +rmi_pci_bus_space_write_multi_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int8_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int8_t *)(handle + offset)) = *addr; + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int16_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int16_t *)(handle + offset)) = bswap16(*addr); + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int32_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int32_t *)(handle + offset)) = bswap32(*addr); + addr++; + } +} + +/* + * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described + * by tag/handle starting at `offset'. + */ + +static void +rmi_pci_bus_space_set_region_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + for (; count != 0; count--, addr += 2) + (*(volatile u_int16_t *)(addr)) = value; +} + +static void +rmi_pci_bus_space_set_region_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + for (; count != 0; count--, addr += 4) + (*(volatile u_int32_t *)(addr)) = value; +} + + +/* + * Copy `count' 1, 2, 4, or 8 byte values from bus space starting + * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. + */ +static void +rmi_pci_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, + bus_size_t off2, size_t count) +{ + TODO(); +} + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle/offset and copy into buffer provided. + */ + +u_int8_t +rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + + return *((volatile u_int8_t *)(handle + offset)); +} + + +static u_int16_t +rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + return *(volatile u_int16_t *)(handle + offset); +} + + +static u_int32_t +rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + return (*(volatile u_int32_t *)(handle + offset)); +} + + +static void +rmi_pci_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, size_t count) +{ + while (count--) { + *addr = (*(volatile u_int8_t *)(handle + offset)); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, size_t count) +{ + while (count--) { + *addr = (*(volatile u_int16_t *)(handle + offset)); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, size_t count) +{ + while (count--) { + *addr = (*(volatile u_int32_t *)(handle + offset)); + addr++; + } +} + + + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle and starting at `offset' and copy into + * buffer provided. + */ +void +rmi_pci_bus_space_read_region_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = (*(volatile u_int8_t *)(baddr)); + baddr += 1; + } +} + +void +rmi_pci_bus_space_read_region_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = (*(volatile u_int16_t *)(baddr)); + baddr += 2; + } +} + +void +rmi_pci_bus_space_read_region_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = (*(volatile u_int32_t *)(baddr)); + baddr += 4; + } +} + + +void +rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int8_t value) +{ + mips_sync(); + *(volatile u_int8_t *)(handle + offset) = value; +} + +static void +rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int16_t value) +{ + mips_sync(); + *(volatile u_int16_t *)(handle + offset) = value; +} + + +static void +rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int32_t value) +{ + mips_sync(); + *(volatile u_int32_t *)(handle + offset) = value; +} + + +static void +rmi_pci_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int8_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int8_t *)(handle + offset)) = *addr; + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int16_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int16_t *)(handle + offset)) = *addr; + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int32_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int32_t *)(handle + offset)) = *addr; + addr++; + } +} + +void +rmi_pci_bus_space_write_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int16_t * addr, + size_t count) +{ + bus_addr_t baddr = (bus_addr_t) bsh + offset; + + while (count--) { + (*(volatile u_int16_t *)(baddr)) = *addr; + addr++; + baddr += 2; + } +} + +void +rmi_pci_bus_space_write_region_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, const u_int32_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + (*(volatile u_int32_t *)(baddr)) = *addr; + addr++; + baddr += 4; + } +} + +static void +rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, + bus_size_t offset __unused, bus_size_t len __unused, int flags) +{ + +} +/*- + * Copyright (c) 2009 RMI Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * */ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); Modified: head/sys/mips/rmi/files.xlr ============================================================================== --- head/sys/mips/rmi/files.xlr Sat Feb 20 17:12:07 2010 (r204135) +++ head/sys/mips/rmi/files.xlr Sat Feb 20 17:19:16 2010 (r204136) @@ -14,10 +14,10 @@ mips/rmi/uart_bus_xlr_iodi.c optional mips/rmi/uart_cpu_mips_xlr.c optional uart mips/rmi/perfmon_kern.c optional xlr_perfmon mips/rmi/perfmon_percpu.c optional xlr_perfmon -#mips/rmi/pcibus.c optional pci -#mips/rmi/xlr_pci.c optional pci +mips/rmi/xlr_pci.c optional pci #mips/rmi/xls_ehci.c optional usb ehci mips/rmi/bus_space_rmi.c standard +mips/rmi/bus_space_rmi_pci.c optional pci mips/rmi/dev/sec/rmisec.c optional rmisec mips/rmi/dev/sec/rmilib.c optional rmisec mips/rmi/dev/xlr/rge.c optional rge Modified: head/sys/mips/rmi/pcibus.h ============================================================================== --- head/sys/mips/rmi/pcibus.h Sat Feb 20 17:12:07 2010 (r204135) +++ head/sys/mips/rmi/pcibus.h Sat Feb 20 17:19:16 2010 (r204136) @@ -25,38 +25,11 @@ * * $FreeBSD$ */ -#define DEFAULT_PCI_CONFIG_BASE 0x18000000 +#define DEFAULT_PCI_CONFIG_BASE 0x18000000 +#define MSI_MIPS_ADDR_BASE 0xfee00000 -#define MSI_MIPS_ADDR_BASE 0xfee00000 +#define PCIE_LINK0_MSI_STATUS 0x90 +#define PCIE_LINK1_MSI_STATUS 0x94 +#define PCIE_LINK2_MSI_STATUS 0x190 +#define PCIE_LINK3_MSI_STATUS 0x194 - -#define PCIE_LINK0_MSI_STATUS 0x90 -#define PCIE_LINK1_MSI_STATUS 0x94 -#define PCIE_LINK2_MSI_STATUS 0x190 -#define PCIE_LINK3_MSI_STATUS 0x194 - -void pci_init_resources(void); -struct resource * -xlr_pci_alloc_resource(device_t bus, device_t child, - int type, int *rid, - u_long start, u_long end, u_long count, - u_int flags); -int -pci_activate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r); -int -pci_deactivate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r); -int -pci_release_resource(device_t bus, device_t child, int type, int rid, - struct resource *r); -struct rman *pci_get_rman(device_t dev, int type); - -int -mips_platform_pci_setup_intr(device_t dev, device_t child, - struct resource *irq, int flags, - driver_filter_t * filt, - driver_intr_t * intr, void *arg, - void **cookiep); -int - mips_pci_route_interrupt(device_t bus, device_t dev, int pin); Modified: head/sys/mips/rmi/xlr_pci.c ============================================================================== --- head/sys/mips/rmi/xlr_pci.c Sat Feb 20 17:12:07 2010 (r204135) +++ head/sys/mips/rmi/xlr_pci.c Sat Feb 20 17:19:16 2010 (r204136) @@ -28,17 +28,21 @@ * * RMI_BSD */ #include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); #include <sys/param.h> -#include <sys/types.h> #include <sys/systm.h> +#include <sys/types.h> #include <sys/kernel.h> #include <sys/module.h> #include <sys/malloc.h> #include <sys/bus.h> +#include <sys/endian.h> #include <machine/bus.h> #include <machine/md_var.h> +#include <machine/intr_machdep.h> #include <mips/rmi/rmi_mips_exts.h> +#include <mips/rmi/interrupt.h> #include <machine/cpuregs.h> #include <vm/vm.h> #include <vm/vm_param.h> @@ -47,50 +51,46 @@ #include <sys/rman.h> #include <dev/pci/pcivar.h> #include <dev/pci/pcireg.h> -#include <dev/pci/pcib_private.h> #include <mips/rmi/iomap.h> #include <mips/rmi/pic.h> #include <mips/rmi/shared_structs.h> #include <mips/rmi/board.h> #include <mips/rmi/pcibus.h> + #include "pcib_if.h" +#define pci_cfg_offset(bus,slot,devfn,where) (((bus)<<16) + ((slot) << 11)+((devfn)<<8)+(where)) +#define PCIE_LINK_STATE 0x4000 + #define LSU_CFG0_REGID 0 #define LSU_CERRLOG_REGID 9 #define LSU_CERROVF_REGID 10 #define LSU_CERRINT_REGID 11 -#define SWAP32(x)\ - (((x) & 0xff000000) >> 24) | \ - (((x) & 0x000000ff) << 24) | \ - (((x) & 0x0000ff00) << 8) | \ - (((x) & 0x00ff0000) >> 8) - /* MSI support */ - -#define MSI_MIPS_ADDR_DEST 0x000ff000 -#define MSI_MIPS_ADDR_RH 0x00000008 -#define MSI_MIPS_ADDR_RH_OFF 0x00000000 -#define MSI_MIPS_ADDR_RH_ON 0x00000008 -#define MSI_MIPS_ADDR_DM 0x00000004 -#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000 -#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004 +#define MSI_MIPS_ADDR_DEST 0x000ff000 +#define MSI_MIPS_ADDR_RH 0x00000008 +#define MSI_MIPS_ADDR_RH_OFF 0x00000000 +#define MSI_MIPS_ADDR_RH_ON 0x00000008 +#define MSI_MIPS_ADDR_DM 0x00000004 +#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000 +#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004 /* Fields in data for Intel MSI messages. */ -#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */ -#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */ -#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */ - -#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */ -#define MSI_MIPS_DATA_DEASSERT 0x00000000 -#define MSI_MIPS_DATA_ASSERT 0x00004000 - -#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */ -#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */ -#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */ +#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */ +#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */ +#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */ + +#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */ +#define MSI_MIPS_DATA_DEASSERT 0x00000000 +#define MSI_MIPS_DATA_ASSERT 0x00004000 + +#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */ +#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */ +#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */ -#define MSI_MIPS_DATA_INTVEC 0x000000ff +#define MSI_MIPS_DATA_INTVEC 0x000000ff /* * Build Intel MSI message and data values from a source. AMD64 systems @@ -104,52 +104,95 @@ (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \ MSI_MIPS_DATA_ASSERT | (irq)) -struct xlr_hose_softc { +#define DEBUG +#ifdef DEBUG +#define dbg_devprintf device_printf +#else +#define dbg_devprintf(dev, fmt, ...) +#endif + +struct xlr_pcib_softc { int junk; /* no softc */ }; + +extern bus_space_tag_t rmi_pci_bus_space; static devclass_t pcib_devclass; -static int pci_bus_status = 0; -static void *pci_config_base; +static void *xlr_pci_config_base; +static struct rman irq_rman, port_rman, mem_rman; -static uint32_t pci_cfg_read_32bit(uint32_t addr); -static void pci_cfg_write_32bit(uint32_t addr, uint32_t data); +static void +xlr_pci_init_resources(void) +{ + irq_rman.rm_start = 0; + irq_rman.rm_end = 255; + irq_rman.rm_type = RMAN_ARRAY; + irq_rman.rm_descr = "PCI Mapped Interrupts"; + if (rman_init(&irq_rman) + || rman_manage_region(&irq_rman, 0, 255)) + panic("pci_init_resources irq_rman"); + + port_rman.rm_start = 0; + port_rman.rm_end = ~0u; + port_rman.rm_type = RMAN_ARRAY; + port_rman.rm_descr = "I/O ports"; + if (rman_init(&port_rman) + || rman_manage_region(&port_rman, 0x10000000, 0x1fffffff)) + panic("pci_init_resources port_rman"); + + mem_rman.rm_start = 0; + mem_rman.rm_end = ~0u; + mem_rman.rm_type = RMAN_ARRAY; + mem_rman.rm_descr = "I/O memory"; + if (rman_init(&mem_rman) + || rman_manage_region(&mem_rman, 0xd0000000, 0xdfffffff)) + panic("pci_init_resources mem_rman"); +} static int xlr_pcib_probe(device_t dev) { - device_set_desc(dev, "xlr system bridge controller"); + if (xlr_board_info.is_xls) + device_set_desc(dev, "XLS PCIe bus"); + else + device_set_desc(dev, "XLR PCI bus"); - pci_init_resources(); - pci_config_base = (void *)MIPS_PHYS_TO_KSEG1(DEFAULT_PCI_CONFIG_BASE); - pci_bus_status = 1; + xlr_pci_init_resources(); + xlr_pci_config_base = (void *)MIPS_PHYS_TO_KSEG1(DEFAULT_PCI_CONFIG_BASE); return 0; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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