Date: Tue, 10 Aug 2021 20:21:23 GMT From: Mitchell Horne <mhorne@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: d78896e46f1d - main - pmc(3): remove Pentium-related man pages and references Message-ID: <202108102021.17AKLN0X036431@gitrepo.freebsd.org>
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The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=d78896e46f1d7744155919476c012400321d0dab commit d78896e46f1d7744155919476c012400321d0dab Author: Mitchell Horne <mhorne@FreeBSD.org> AuthorDate: 2021-08-10 20:19:58 +0000 Commit: Mitchell Horne <mhorne@FreeBSD.org> CommitDate: 2021-08-10 20:19:58 +0000 pmc(3): remove Pentium-related man pages and references Support for Pentium events was removed completely in e92a1350b50e. Don't bump .Dd where we are just removing xrefs. Reviewed by: emaste MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D31423 --- ObsoleteFiles.inc | 5 + lib/libpmc/Makefile | 3 - lib/libpmc/pmc.3 | 47 +- lib/libpmc/pmc.atom.3 | 3 - lib/libpmc/pmc.atomsilvermont.3 | 3 - lib/libpmc/pmc.core.3 | 3 - lib/libpmc/pmc.core2.3 | 3 - lib/libpmc/pmc.corei7.3 | 3 - lib/libpmc/pmc.corei7uc.3 | 3 - lib/libpmc/pmc.haswell.3 | 3 - lib/libpmc/pmc.haswelluc.3 | 3 - lib/libpmc/pmc.haswellxeon.3 | 3 - lib/libpmc/pmc.iaf.3 | 3 - lib/libpmc/pmc.ivybridge.3 | 3 - lib/libpmc/pmc.ivybridgexeon.3 | 3 - lib/libpmc/pmc.k7.3 | 3 - lib/libpmc/pmc.k8.3 | 3 - lib/libpmc/pmc.mips24k.3 | 3 - lib/libpmc/pmc.octeon.3 | 3 - lib/libpmc/pmc.p4.3 | 1223 -------------------------------------- lib/libpmc/pmc.p5.3 | 460 -------------- lib/libpmc/pmc.p6.3 | 1026 -------------------------------- lib/libpmc/pmc.sandybridge.3 | 3 - lib/libpmc/pmc.sandybridgeuc.3 | 3 - lib/libpmc/pmc.sandybridgexeon.3 | 3 - lib/libpmc/pmc.soft.3 | 3 - lib/libpmc/pmc.tsc.3 | 3 - lib/libpmc/pmc.ucf.3 | 3 - lib/libpmc/pmc.westmere.3 | 3 - lib/libpmc/pmc.westmereuc.3 | 3 - 30 files changed, 6 insertions(+), 2830 deletions(-) diff --git a/ObsoleteFiles.inc b/ObsoleteFiles.inc index 99db0e591090..db8441716091 100644 --- a/ObsoleteFiles.inc +++ b/ObsoleteFiles.inc @@ -40,6 +40,11 @@ # xargs -n1 | sort | uniq -d; # done +# 20210810: remove Pentium-related man pages and references +OLD_FILES+=usr/share/man/man3/pmc.p4.3.gz +OLD_FILES+=usr/share/man/man3/pmc.p5.3.gz +OLD_FILES+=usr/share/man/man3/pmc.p6.3.gz + # 20210805: C.UTF-8 installed to the wrong location OLD_FILES+=usr/share/C.UTF-8.LC_CTYPE diff --git a/lib/libpmc/Makefile b/lib/libpmc/Makefile index 285b6c539ece..2ef0d288064c 100644 --- a/lib/libpmc/Makefile +++ b/lib/libpmc/Makefile @@ -83,9 +83,6 @@ MAN+= pmc.k7.3 MAN+= pmc.k8.3 MAN+= pmc.mips24k.3 MAN+= pmc.octeon.3 -MAN+= pmc.p4.3 -MAN+= pmc.p5.3 -MAN+= pmc.p6.3 MAN+= pmc.sandybridge.3 MAN+= pmc.sandybridgeuc.3 MAN+= pmc.sandybridgexeon.3 diff --git a/lib/libpmc/pmc.3 b/lib/libpmc/pmc.3 index c70862668980..4bf2907db129 100644 --- a/lib/libpmc/pmc.3 +++ b/lib/libpmc/pmc.3 @@ -23,7 +23,7 @@ .\" .\" $FreeBSD$ .\" -.Dd December 12, 2020 +.Dd August 10, 2021 .Dt PMC 3 .Os .Sh NAME @@ -161,26 +161,6 @@ and CPUs, and other CPUs conforming to version 2 of the .Tn Intel performance measurement architecture. -.It Li PMC_CPU_INTEL_P5 -.Tn Intel -.Tn "Pentium" -CPUs. -.It Li PMC_CPU_INTEL_P6 -.Tn Intel -.Tn "Pentium Pro" -CPUs. -.It Li PMC_CPU_INTEL_PII -.Tn "Intel Pentium II" -CPUs. -.It Li PMC_CPU_INTEL_PIII -.Tn "Intel Pentium III" -CPUs. -.It Li PMC_CPU_INTEL_PIV -.Tn "Intel Pentium 4" -CPUs. -.It Li PMC_CPU_INTEL_PM -.Tn "Intel Pentium M" -CPUs. .El .Ss Supported PMCs PMC supported by this library are named by the @@ -205,25 +185,6 @@ CPUs. Programmable hardware counters present in .Tn "AMD Athlon64" CPUs. -.It Li PMC_CLASS_P4 -Programmable hardware counters present in -.Tn "Intel Pentium 4" -CPUs. -.It Li PMC_CLASS_P5 -Programmable hardware counters present in -.Tn Intel -.Tn Pentium -CPUs. -.It Li PMC_CLASS_P6 -Programmable hardware counters present in -.Tn Intel -.Tn "Pentium Pro" , -.Tn "Pentium II" , -.Tn "Pentium III" , -.Tn "Celeron" , -and -.Tn "Pentium M" -CPUs. .It Li PMC_CLASS_TSC The timestamp counter on i386 and amd64 architecture CPUs. .It Li PMC_CLASS_SOFT @@ -473,9 +434,6 @@ following manual pages: .It Li PMC_CLASS_IAP Ta Xr pmc.atom 3 , Xr pmc.core 3 , Xr pmc.core2 3 .It Li PMC_CLASS_K7 Ta Xr pmc.k7 3 .It Li PMC_CLASS_K8 Ta Xr pmc.k8 3 -.It Li PMC_CLASS_P4 Ta Xr pmc.p4 3 -.It Li PMC_CLASS_P5 Ta Xr pmc.p5 3 -.It Li PMC_CLASS_P6 Ta Xr pmc.p6 3 .It Li PMC_CLASS_TSC Ta Xr pmc.tsc 3 .El .Ss Event Name Aliases @@ -535,9 +493,6 @@ API is .Xr pmc.k8 3 , .Xr pmc.mips24k 3 , .Xr pmc.octeon 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , diff --git a/lib/libpmc/pmc.atom.3 b/lib/libpmc/pmc.atom.3 index edf81ba54a5e..a79d14c9d4c1 100644 --- a/lib/libpmc/pmc.atom.3 +++ b/lib/libpmc/pmc.atom.3 @@ -1174,9 +1174,6 @@ and the underlying hardware events used on these CPUs. .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , diff --git a/lib/libpmc/pmc.atomsilvermont.3 b/lib/libpmc/pmc.atomsilvermont.3 index 7ed9de461e33..dd1f66a429c7 100644 --- a/lib/libpmc/pmc.atomsilvermont.3 +++ b/lib/libpmc/pmc.atomsilvermont.3 @@ -512,9 +512,6 @@ The number of times the MSROM starts a flow of UOPS. .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , diff --git a/lib/libpmc/pmc.core.3 b/lib/libpmc/pmc.core.3 index 551e615dc320..8d922cf3c1af 100644 --- a/lib/libpmc/pmc.core.3 +++ b/lib/libpmc/pmc.core.3 @@ -789,9 +789,6 @@ may not count some transitions. .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmclog 3 , diff --git a/lib/libpmc/pmc.core2.3 b/lib/libpmc/pmc.core2.3 index cd038fb411d9..7c7049136c2b 100644 --- a/lib/libpmc/pmc.core2.3 +++ b/lib/libpmc/pmc.core2.3 @@ -1104,9 +1104,6 @@ and the underlying hardware events used. .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , diff --git a/lib/libpmc/pmc.corei7.3 b/lib/libpmc/pmc.corei7.3 index e9e2a6e61784..0c405d8e6e7f 100644 --- a/lib/libpmc/pmc.corei7.3 +++ b/lib/libpmc/pmc.corei7.3 @@ -1583,9 +1583,6 @@ Counts number of segment register loads. .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , diff --git a/lib/libpmc/pmc.corei7uc.3 b/lib/libpmc/pmc.corei7uc.3 index 1f49222ceda6..a102a7b6c1b3 100644 --- a/lib/libpmc/pmc.corei7uc.3 +++ b/lib/libpmc/pmc.corei7uc.3 @@ -886,9 +886,6 @@ into a power down mode. .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , diff --git a/lib/libpmc/pmc.haswell.3 b/lib/libpmc/pmc.haswell.3 index c69d4b694ca2..c858c702fdf1 100644 --- a/lib/libpmc/pmc.haswell.3 +++ b/lib/libpmc/pmc.haswell.3 @@ -921,9 +921,6 @@ Dirty L2 cache lines evicted by demand. .Xr pmc.ivybridgexeon 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , diff --git a/lib/libpmc/pmc.haswelluc.3 b/lib/libpmc/pmc.haswelluc.3 index e7b57c59d0e5..a067a75201ce 100644 --- a/lib/libpmc/pmc.haswelluc.3 +++ b/lib/libpmc/pmc.haswelluc.3 @@ -205,9 +205,6 @@ Number of requests allocated in Coherency Tracker. .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , diff --git a/lib/libpmc/pmc.haswellxeon.3 b/lib/libpmc/pmc.haswellxeon.3 index 5f9a5b20eb5c..7610775adcb3 100644 --- a/lib/libpmc/pmc.haswellxeon.3 +++ b/lib/libpmc/pmc.haswellxeon.3 @@ -935,9 +935,6 @@ Dirty L2 cache lines evicted by demand. .Xr pmc.ivybridgexeon 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , diff --git a/lib/libpmc/pmc.iaf.3 b/lib/libpmc/pmc.iaf.3 index f80560999f46..fcfa98042aaf 100644 --- a/lib/libpmc/pmc.iaf.3 +++ b/lib/libpmc/pmc.iaf.3 @@ -128,9 +128,6 @@ CPU, use the event specifier .Xr pmc.core2 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , diff --git a/lib/libpmc/pmc.ivybridge.3 b/lib/libpmc/pmc.ivybridge.3 index d86199b4d407..938d2947a844 100644 --- a/lib/libpmc/pmc.ivybridge.3 +++ b/lib/libpmc/pmc.ivybridge.3 @@ -833,9 +833,6 @@ Dirty L2 cache lines evicted by the MLC prefetcher. .Xr pmc.ivybridgexeon 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , diff --git a/lib/libpmc/pmc.ivybridgexeon.3 b/lib/libpmc/pmc.ivybridgexeon.3 index 1bbe16039bd2..9bcf4dbd56da 100644 --- a/lib/libpmc/pmc.ivybridgexeon.3 +++ b/lib/libpmc/pmc.ivybridgexeon.3 @@ -866,9 +866,6 @@ Dirty L2 cache lines filling the L2. .Xr pmc.ivybridge 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , diff --git a/lib/libpmc/pmc.k7.3 b/lib/libpmc/pmc.k7.3 index a8be8143f9ea..42933f1958fb 100644 --- a/lib/libpmc/pmc.k7.3 +++ b/lib/libpmc/pmc.k7.3 @@ -246,9 +246,6 @@ and the underlying hardware events used. .Xr pmc.core2 3 , .Xr pmc.iaf 3 , .Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmclog 3 , diff --git a/lib/libpmc/pmc.k8.3 b/lib/libpmc/pmc.k8.3 index 45c70baa438c..cbfe617f31b1 100644 --- a/lib/libpmc/pmc.k8.3 +++ b/lib/libpmc/pmc.k8.3 @@ -779,9 +779,6 @@ and the underlying hardware events used. .Xr pmc.core2 3 , .Xr pmc.iaf 3 , .Xr pmc.k7 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmclog 3 , diff --git a/lib/libpmc/pmc.mips24k.3 b/lib/libpmc/pmc.mips24k.3 index d886d0e8c906..52761d5db751 100644 --- a/lib/libpmc/pmc.mips24k.3 +++ b/lib/libpmc/pmc.mips24k.3 @@ -389,9 +389,6 @@ and the underlying hardware events used. .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.octeon 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , diff --git a/lib/libpmc/pmc.octeon.3 b/lib/libpmc/pmc.octeon.3 index 019b448522e9..43d204f164e6 100644 --- a/lib/libpmc/pmc.octeon.3 +++ b/lib/libpmc/pmc.octeon.3 @@ -229,9 +229,6 @@ and the underlying hardware events used. .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.mips24k 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , diff --git a/lib/libpmc/pmc.p4.3 b/lib/libpmc/pmc.p4.3 deleted file mode 100644 index e113b72001e1..000000000000 --- a/lib/libpmc/pmc.p4.3 +++ /dev/null @@ -1,1223 +0,0 @@ -.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved. -.\" -.\" Redistribution and use in source and binary forms, with or without -.\" modification, are permitted provided that the following conditions -.\" are met: -.\" 1. Redistributions of source code must retain the above copyright -.\" notice, this list of conditions and the following disclaimer. -.\" 2. Redistributions in binary form must reproduce the above copyright -.\" notice, this list of conditions and the following disclaimer in the -.\" documentation and/or other materials provided with the distribution. -.\" -.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -.\" SUCH DAMAGE. -.\" -.\" $FreeBSD$ -.\" -.Dd October 4, 2008 -.Dt PMC.P4 3 -.Os -.Sh NAME -.Nm pmc.p4 -.Nd measurement events for -.Tn "Intel Pentium 4" -and other -.Tn Netburst -architecture CPUs -.Sh LIBRARY -.Lb libpmc -.Sh SYNOPSIS -.In pmc.h -.Sh DESCRIPTION -Intel P4 PMCs are present in Intel -.Tn "Pentium 4" -and -.Tn Xeon -processors that use the -.Tn Netburst -CPU architecture. -.Pp -These PMCs are documented in -.Rs -.%B "IA-32 Intel(R) Architecture Software Developer's Manual" -.%T "Volume 3: System Programming Guide" -.%N "Order Number 245472-012" -.%D 2003 -.%Q "Intel Corporation" -.Re -Further information about using these PMCs may be found in -.Rs -.%B "IA-32 Intel(R) Architecture Optimization Guide" -.%D 2003 -.%N "Order Number 248966-009" -.%Q "Intel Corporation" -.Re -Some of these events are affected by processor errata described in -.Rs -.%B "Intel(R) Pentium(R) 4 Processor Specification Update" -.%N "Document Number: 249199-059" -.%D "April 2005" -.%Q "Intel Corporation" -.Re -.Ss PMC Features -Intel Pentium 4 PMCs are 40 bits wide. -Each CPU contains 18 PMCs, divided into 4 groups with 4, 4, 4 and 6 -PMCs respectively. -On processors with hyperthreading support, PMC resources are shared -between logical processors. -These PMCs support the following capabilities: -.Bl -column "PMC_CAP_INTERRUPT" "Support" -.It Em Capability Ta Em Support -.It PMC_CAP_CASCADE Ta Yes -.It PMC_CAP_EDGE Ta Yes -.It PMC_CAP_INTERRUPT Ta Yes -.It PMC_CAP_INVERT Ta Yes -.It PMC_CAP_READ Ta Yes -.It PMC_CAP_PRECISE Ta Unimplemented -.It PMC_CAP_SYSTEM Ta Yes -.It PMC_CAP_TAGGING Ta Yes -.It PMC_CAP_THRESHOLD Ta Yes -.It PMC_CAP_USER Ta Yes -.It PMC_CAP_WRITE Ta Yes -.El -.Ss Event Qualifiers -Event specifiers for Intel P4 PMCs can have the following common -qualifiers: -.Bl -tag -width indent -.It Li active= Ns Ar choice -(On P4 HTT CPUs) Filter event counting based on which logical -processors are active. -The allowed values of -.Ar choice -are: -.Pp -.Bl -tag -width indent -compact -.It Li any -Count when either logical processor is active. -.It Li both -Count when both logical processors are active. -.It Li none -Count only when neither logical processor is active. -.It Li single -Count only when one logical processor is active. -.El -.Pp -The default is -.Dq Li both . -.It Li cascade -Configure the PMC to cascade onto its partner. -See -.Sx "Cascading P4 PMCs" -below for more information. -.It Li edge -Configure the counter to count false to true transitions of the threshold -comparison output. -This qualifier only takes effect if a threshold qualifier has also been -specified. -.It Li complement -Configure the counter to increment only when the event count seen is -less than the threshold qualifier value specified. -.It Li mask= Ns Ar qualifier -Many event specifiers for Intel P4 PMCs need to be additionally -qualified using a mask qualifier. -The allowed syntax for these qualifiers is event specific and is -described along with the events. -.It Li os -Configure the PMC to count when the CPL of the processor is 0. -.It Li precise -Select precise event based sampling. -Precise sampling is supported by the hardware for a limited set of -events. -.It Li tag= Ns Ar value -Configure the PMC to tag the internal uop selected by the other -fields in this event specifier with value -.Ar value . -This feature is used when cascading PMCs. -.It Li threshold= Ns Ar value -Configure the PMC to increment only when the event counts seen are -greater than the specified threshold value -.Ar value . -.It Li usr -Configure the PMC to count when the CPL of the processor is 1, 2 or 3. -.El -.Pp -If neither of the -.Dq Li os -or -.Dq Li usr -qualifiers are specified, the default is to enable both. -.Pp -On Intel Pentium 4 processors with HTT, events are -divided into two classes: -.Pp -.Bl -tag -width indent -compact -.It "TS Events" -are those where hardware can differentiate between events -generated on one logical processor from those generated on the -other. -.It "TI Events" -are those where hardware cannot differentiate between events -generated by multiple logical processors in a package. -.El -.Pp -Only TS events are allowed for use with process-mode PMCs on -Pentium-4/HTT CPUs. -.Pp -The event specifiers supported by Intel P4 PMCs are: -.Bl -tag -width indent -.It Li p4-128bit-mmx-uop Op Li ,mask= Ns Ar flags -.Pq "TI event" -Count integer SIMD SSE2 instructions that operate on 128 bit SIMD -operands. -Qualifier -.Ar flags -can take the following value (which is also the default): -.Pp -.Bl -tag -width indent -compact -.It Li all -Count all uops operating on 128 bit SIMD integer operands in memory or -XMM register. -.El -.Pp -If an instruction contains more than one 128 bit MMX uop, then each -uop will be counted. -.It Li p4-64bit-mmx-uop Op Li ,mask= Ns Ar flags -.Pq "TI event" -Count MMX instructions that operate on 64 bit SIMD operands. -Qualifier -.Ar flags -can take the following value (which is also the default): -.Pp -.Bl -tag -width indent -compact -.It Li all -Count all uops operating on 64 bit SIMD integer operands in memory or -in MMX registers. -.El -.Pp -If an instruction contains more than one 64 bit MMX uop, then each -uop will be counted. -.It Li p4-b2b-cycles -.Pq "TI event" -Count back-to-back bus cycles. -Further documentation for this event is unavailable. -.It Li p4-bnr -.Pq "TI event" -Count bus-not-ready conditions. -Further documentation for this event is unavailable. -.It Li p4-bpu-fetch-request Op Li ,mask= Ns Ar qualifier -.Pq "TS event" -Count instruction fetch requests qualified by additional -flags specified in -.Ar qualifier . -At this point only one flag is supported: -.Pp -.Bl -tag -width indent -compact -.It Li tcmiss -Count trace cache lookup misses. -.El -.Pp -The default qualifier is also -.Dq Li mask=tcmiss . -.It Li p4-branch-retired Op Li ,mask= Ns Ar flags -.Pq "TS event" -Counts retired branches. -Qualifier -.Ar flags -is a list of the following -.Ql + -separated strings: -.Pp -.Bl -tag -width indent -compact -.It Li mmnp -Count branches not-taken and predicted. -.It Li mmnm -Count branches not-taken and mis-predicted. -.It Li mmtp -Count branches taken and predicted. -.It Li mmtm -Count branches taken and mis-predicted. -.El -.Pp -The default qualifier counts all four kinds of branches. -.It Li p4-bsq-active-entries Op Li ,mask= Ns Ar qualifier -.Pq "TS event" -Count the number of entries (clipped at 15) currently active in the -BSQ. -Qualifier -.Ar qualifier -is a -.Ql + -separated set of the following flags: -.Pp -.Bl -tag -width indent -compact -.It Li req-type0 , Li req-type1 -Forms a 2-bit number used to select the request type encoding: -.Pp -.Bl -tag -width indent -compact -.It Li 0 -reads excluding read invalidate -.It Li 1 -read invalidates -.It Li 2 -writes other than writebacks -.It Li 3 -writebacks -.El -.Pp -Bit -.Dq Li req-type1 -is the MSB for this two bit number. -.It Li req-len0 , Li req-len1 -Forms a two-bit number that specifies the request length encoding: -.Pp -.Bl -tag -width indent -compact -.It Li 0 -0 chunks -.It Li 1 -1 chunk -.It Li 3 -8 chunks -.El -.Pp -Bit -.Dq Li req-len1 -is the MSB for this two bit number. -.It Li req-io-type -Count requests that are input or output requests. -.It Li req-lock-type -Count requests that lock the bus. -.It Li req-lock-cache -Count requests that lock the cache. -.It Li req-split-type -Count requests that is a bus 8-byte chunk that is split across an -8-byte boundary. -.It Li req-dem-type -Count requests that are demand (not prefetches) if set. -Count requests that are prefetches if not set. -.It Li req-ord-type -Count requests that are ordered. -.It Li mem-type0 , Li mem-type1 , Li mem-type2 -Forms a 3-bit number that specifies a memory type encoding: -.Pp -.Bl -tag -width indent -compact -.It Li 0 -UC -.It Li 1 -USWC -.It Li 4 -WT -.It Li 5 -WP -.It Li 6 -WB -.El -.Pp -Bit -.Dq Li mem-type2 -is the MSB of this 3-bit number. -.El -.Pp -The default qualifier has all the above bits set. -.Pp -Edge triggering using the -.Dq Li edge -qualifier should not be used with this event when counting cycles. -.It Li p4-bsq-allocation Op Li ,mask= Ns Ar qualifier -.Pq "TS event" -Count allocations in the bus sequence unit according to the flags -specified in -.Ar qualifier , -which is a -.Ql + -separated set of the following flags: -.Pp -.Bl -tag -width indent -compact -.It Li req-type0 , Li req-type1 -Forms a 2-bit number used to select the request type encoding: -.Pp -.Bl -tag -width indent -compact -.It Li 0 -reads excluding read invalidate -.It Li 1 -read invalidates -.It Li 2 -writes other than writebacks -.It Li 3 -writebacks -.El -.Pp -Bit -.Dq Li req-type1 -is the MSB for this two bit number. -.It Li req-len0 , Li req-len1 -Forms a two-bit number that specifies the request length encoding: -.Pp -.Bl -tag -width indent -compact -.It Li 0 -0 chunks -.It Li 1 -1 chunk -.It Li 3 -8 chunks -.El -.Pp -Bit -.Dq Li req-len1 -is the MSB for this two bit number. -.It Li req-io-type -Count requests that are input or output requests. -.It Li req-lock-type -Count requests that lock the bus. -.It Li req-lock-cache -Count requests that lock the cache. -.It Li req-split-type -Count requests that is a bus 8-byte chunk that is split across an -8-byte boundary. -.It Li req-dem-type -Count requests that are demand (not prefetches) if set. -Count requests that are prefetches if not set. -.It Li req-ord-type -Count requests that are ordered. -.It Li mem-type0 , Li mem-type1 , Li mem-type2 -Forms a 3-bit number that specifies a memory type encoding: -.Pp -.Bl -tag -width indent -compact -.It Li 0 -UC -.It Li 1 -USWC -.It Li 4 -WT -.It Li 5 -WP -.It Li 6 -WB -.El -.Pp -Bit -.Dq Li mem-type2 -is the MSB of this 3-bit number. -.El -.Pp -The default qualifier has all the above bits set. -.Pp -This event is usually used along with the -.Dq Li edge -qualifier to avoid multiple counting. -.It Li p4-bsq-cache-reference Op Li ,mask= Ns Ar qualifier -.Pq "TS event" -Count cache references as seen by the bus unit (2nd or 3rd level -cache references). -Qualifier -.Ar qualifier -is a -.Ql + -separated list of the following keywords: -.Pp -.Bl -tag -width indent -compact -.It Li rd-2ndl-hits -Count 2nd level cache hits in the shared state. -.It Li rd-2ndl-hite -Count 2nd level cache hits in the exclusive state. -.It Li rd-2ndl-hitm -Count 2nd level cache hits in the modified state. -.It Li rd-3rdl-hits -Count 3rd level cache hits in the shared state. -.It Li rd-3rdl-hite -Count 3rd level cache hits in the exclusive state. -.It Li rd-3rdl-hitm -Count 3rd level cache hits in the modified state. -.It Li rd-2ndl-miss -Count 2nd level cache misses. -.It Li rd-3rdl-miss -Count 3rd level cache misses. -.It Li wr-2ndl-miss -Count write-back lookups from the data access cache that miss the 2nd -level cache. -.El -.Pp -The default is to count all the above events. -.It Li p4-execution-event Op Li ,mask= Ns Ar flags -.Pq "TS event" -Count the retirement of tagged uops selected through the execution -tagging mechanism. -Qualifier -.Ar flags -can contain the following strings separated by -.Ql + -characters: -.Pp -.Bl -tag -width indent -compact -.It Li nbogus0 , Li nbogus1 , Li nbogus2 , Li nbogus3 -The marked uops are not bogus. -.It Li bogus0 , Li bogus1 , Li bogus2 , Li bogus3 -The marked uops are bogus. -.El -.Pp -This event requires additional (upstream) events to be allocated to -perform the desired uop tagging. -The default is to set all the above flags. -This event can be used for precise event based sampling. -.It Li p4-front-end-event Op Li ,mask= Ns Ar flags -.Pq "TS event" -Count the retirement of tagged uops selected through the front-end -tagging mechanism. -Qualifier -.Ar flags -can contain the following strings separated by -.Ql + -characters: -.Pp -.Bl -tag -width indent -compact -.It Li nbogus -The marked uops are not bogus. -.It Li bogus -The marked uops are bogus. -.El -.Pp -This event requires additional (upstream) events to be allocated to -perform the desired uop tagging. -The default is to select both kinds of events. -This event can be used for precise event based sampling. -.It Li p4-fsb-data-activity Op Li ,mask= Ns Ar flags -.Pq "TI event" -Count each DBSY or DRDY event selected by qualifier -.Ar flags . -Qualifier -.Ar flags -is a -.Ql + -separated set of the following flags: -.Pp -.Bl -tag -width indent -compact -.It Li drdy-drv -Count when this processor is driving data onto the bus. -.It Li drdy-own -Count when this processor is reading data from the bus. -.It Li drdy-other -Count when data is on the bus but not being sampled by this processor. -.It Li dbsy-drv -Count when this processor reserves the bus for use in the next cycle -in order to drive data. -.It Li dbsy-own -Count when some agent reserves the bus for use in the next bus cycle -to drive data that this processor will sample. -.It Li dbsy-other -Count when some agent reserves the bus for use in the next bus cycle -to drive data that this processor will not sample. -.El -.Pp -Flags -.Dq Li drdy-own -and -.Dq Li drdy-other -are mutually exclusive. -Flags -.Dq Li dbsy-own -and -.Dq Li dbsy-other -are mutually exclusive. -The default value for -.Ar qualifier -is -.Dq Li drdy-drv+drdy-own+dbsy-drv+dbsy-own . -.It Li p4-global-power-events Op Li ,mask= Ns Ar flags -.Pq "TS event" -Count cycles during which the processor is not stopped. -Qualifier -.Ar flags -can take the following value (which is also the default): -.Pp -.Bl -tag -width indent -compact -.It Li running -Count cycles when the processor is active. -.El -.It Li p4-instr-retired Op Li ,mask= Ns Ar flags -.Pq "TS event" -Count instructions retired during a clock cycle. -Qualifier -.Ar flags -comprises of the following strings separated by -.Ql + -characters: -.Pp -.Bl -tag -width indent -compact -.It Li nbogusntag -Count non-bogus instructions that are not tagged. -.It Li nbogustag -Count non-bogus instructions that are tagged. -.It Li bogusntag -Count bogus instructions that are not tagged. -.It Li bogustag -Count bogus instructions that are tagged. -.El -.Pp -The default qualifier counts all the above kinds of instructions. -.It Li p4-ioq-active-entries Xo -.Op Li ,mask= Ns Ar qualifier -.Op Li ,busreqtype= Ns Ar req-type -.Xc -.Pq "TS event" -Count the number of entries (clipped at 15) in the IOQ that are -active. -The event masks are specified by qualifier -.Ar qualifier -and -.Ar req-type . -.Pp -Qualifier -.Ar qualifier -is a -.Ql + -separated set of the following flags: -.Pp -.Bl -tag -width indent -compact -.It Li all-read -Count read entries. -.It Li all-write -Count write entries. -.It Li mem-uc *** 2245 LINES SKIPPED ***
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