Date: Sun, 22 Jun 2003 13:36:57 +0200 From: Tilman Linneweh <arved@FreeBSD.org> To: freebsd-gnats-submit@FreeBSD.org, thorsten.greiner@consol.de Cc: FreeBSD-bugs@FreeBSD.org Subject: Re: kern/33004: Patch for USB (uhci) Message-ID: <200306221336.57346.arved@FreeBSD.org>
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Hi, [ Joe, I am CCing you, since you have done most of the USB stuff in CURRENT ] Today I upgraded my Notebook to 5.1, and this patch is still necessary to get USB working. Relevant parts of dmesg with patch: uhci0: <Intel 82443MX USB controller> port 0x1c00-0x1c1f irq 11 at device 7.2 on pci0 usb0: <Intel 82443MX USB controller> on uhci0 usb0: USB revision 1.0 uhub0: Intel UHCI root hub, class 9/0, rev 1.00/1.00, addr 1 uhub0: 2 ports with 2 removable, self powered ums0: Cypress Sem Cypress USB Mouse, rev 1.00/4.9c, addr 2, iclass 3/1 ums0: 3 buttons and Z dir. without patch: uhci0: <Intel 82443MX USB controller> port 0x1c00-0x1c1f irq 11 at device 7.2 on pci0 usb0: <Intel 82443MX USB controller> on uhci0 usb0: USB revision 1.0 uhub0: Intel UHCI root hub, class 9/0, rev 1.00/1.00, addr 1 uhub0: 2 ports with 2 removable, self powered uhub0: device problem, disabling port 1 Some things changed since Thorsten submitted the patch, so here is a diff relative to CURRENT. Since PCI_COMMAND_STATUS_REG has been removed in CURRENT, I defined it, but probably PCIR_COMMAND should be used, but neither am I a PCI hacker nor did I found any documentation about the purpose of this defines. regards tilman Index: uhci_pci.c =================================================================== RCS file: /home/ncvs/src/sys/dev/usb/uhci_pci.c,v retrieving revision 1.47 diff -u -r1.47 uhci_pci.c --- uhci_pci.c 12 Jun 2003 05:29:15 -0000 1.47 +++ uhci_pci.c 22 Jun 2003 11:17:58 -0000 @@ -138,7 +138,7 @@ static const char *uhci_device_generic = "UHCI (generic) USB controller"; #define PCI_UHCI_BASE_REG 0x20 - +#define PCI_COMMAND_STATUS_REG 0x04 static int uhci_pci_attach(device_t self); static int uhci_pci_detach(device_t self); @@ -164,8 +164,13 @@ uhci_pci_resume(device_t self) { uhci_softc_t *sc = device_get_softc(self); + u_int32_t csr; uhci_power(PWR_RESUME, sc); + /* Enable the device. */ + csr = pci_read_config(self, PCI_COMMAND_STATUS_REG, 4); + pci_write_config(self, PCI_COMMAND_STATUS_REG, + csr | PCIM_CMD_BUSMASTEREN, 4); bus_generic_resume(self); return 0; @@ -244,6 +249,7 @@ uhci_softc_t *sc = device_get_softc(self); int rid; int err; + u_int32_t csr; pci_enable_busmaster(self); @@ -304,6 +310,11 @@ sc->sc_bus.usbrev = USBREV_UNKNOWN; break; } + + /* Enable the device. */ + csr = pci_read_config(self, PCI_COMMAND_STATUS_REG, 4); + pci_write_config(self, PCI_COMMAND_STATUS_REG, + csr | PCIM_CMD_BUSMASTEREN, 4); err = bus_setup_intr(self, sc->irq_res, INTR_TYPE_BIO, (driver_intr_t *) uhci_intr, sc, &sc->ih);
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