Date: Thu, 24 May 2018 04:30:06 +0000 (UTC) From: Matt Macy <mmacy@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r334128 - in head: . lib/libpmcstat lib/libpmcstat/pmu-events lib/libpmcstat/pmu-events/arch lib/libpmcstat/pmu-events/arch/arm64 lib/libpmcstat/pmu-events/arch/arm64/arm lib/libpmcstat... Message-ID: <201805240430.w4O4U6Js001134@repo.freebsd.org>
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Author: mmacy Date: Thu May 24 04:30:06 2018 New Revision: 334128 URL: https://svnweb.freebsd.org/changeset/base/334128 Log: libpmcstat: compile in events based on json description Added: head/lib/libpmcstat/libpmcstat_pmu_util.c (contents, props changed) head/lib/libpmcstat/pmu-events/ head/lib/libpmcstat/pmu-events/Makefile (contents, props changed) head/lib/libpmcstat/pmu-events/README (contents, props changed) head/lib/libpmcstat/pmu-events/arch/ head/lib/libpmcstat/pmu-events/arch/arm64/ head/lib/libpmcstat/pmu-events/arch/arm64/arm/ head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/ head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/branch.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/bus.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/arm64/armv8-recommended.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/arm64/cavium/ head/lib/libpmcstat/pmu-events/arch/arm64/cavium/thunderx2/ head/lib/libpmcstat/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/arm64/hisilicon/ head/lib/libpmcstat/pmu-events/arch/arm64/hisilicon/hip08/ head/lib/libpmcstat/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/arm64/mapfile.csv (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/ head/lib/libpmcstat/pmu-events/arch/powerpc/mapfile.csv (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power8/ head/lib/libpmcstat/pmu-events/arch/powerpc/power8/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power8/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power8/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power8/marked.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power8/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power8/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power8/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power8/pmc.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power8/translation.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power9/ head/lib/libpmcstat/pmu-events/arch/powerpc/power9/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power9/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power9/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power9/marked.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power9/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power9/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power9/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power9/pmc.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/powerpc/power9/translation.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/ head/lib/libpmcstat/pmu-events/arch/s390/cf_z10/ head/lib/libpmcstat/pmu-events/arch/s390/cf_z10/basic.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_z10/crypto.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_z10/extended.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_z13/ head/lib/libpmcstat/pmu-events/arch/s390/cf_z13/basic.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_z13/crypto.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_z13/extended.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_z14/ head/lib/libpmcstat/pmu-events/arch/s390/cf_z14/basic.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_z14/crypto.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_z14/extended.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_z196/ head/lib/libpmcstat/pmu-events/arch/s390/cf_z196/basic.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_z196/crypto.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_z196/extended.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_zec12/ head/lib/libpmcstat/pmu-events/arch/s390/cf_zec12/basic.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_zec12/crypto.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/cf_zec12/extended.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/s390/mapfile.csv (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ head/lib/libpmcstat/pmu-events/arch/x86/bonnell/ head/lib/libpmcstat/pmu-events/arch/x86/bonnell/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/bonnell/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/bonnell/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/bonnell/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/bonnell/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/bonnell/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/bonnell/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwell/ head/lib/libpmcstat/pmu-events/arch/x86/broadwell/bdw-metrics.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwell/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwell/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwell/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwell/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwell/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwell/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwell/uncore.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwell/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/ head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/bdwde-metrics.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/uncore-cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/uncore-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/uncore-power.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellde/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/ head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/bdx-metrics.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/uncore-cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/uncore-interconnect.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/uncore-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/uncore-power.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/broadwellx/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmont/ head/lib/libpmcstat/pmu-events/arch/x86/goldmont/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmont/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmont/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmont/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmont/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmont/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmontplus/ head/lib/libpmcstat/pmu-events/arch/x86/goldmontplus/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmontplus/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmontplus/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmontplus/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmontplus/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/goldmontplus/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswell/ head/lib/libpmcstat/pmu-events/arch/x86/haswell/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswell/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswell/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswell/hsw-metrics.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswell/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswell/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswell/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswell/uncore.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswell/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/ head/lib/libpmcstat/pmu-events/arch/x86/haswellx/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/hsx-metrics.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/uncore-cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/uncore-interconnect.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/uncore-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/uncore-power.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/haswellx/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivybridge/ head/lib/libpmcstat/pmu-events/arch/x86/ivybridge/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivybridge/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivybridge/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivybridge/ivb-metrics.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivybridge/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivybridge/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivybridge/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivybridge/uncore.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivybridge/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/ head/lib/libpmcstat/pmu-events/arch/x86/ivytown/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/ivt-metrics.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/uncore-cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/uncore-interconnect.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/uncore-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/uncore-power.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/ivytown/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/ head/lib/libpmcstat/pmu-events/arch/x86/jaketown/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/jkt-metrics.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/uncore-cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/uncore-interconnect.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/uncore-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/uncore-power.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/jaketown/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/knightslanding/ head/lib/libpmcstat/pmu-events/arch/x86/knightslanding/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/knightslanding/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/knightslanding/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/knightslanding/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/knightslanding/uncore-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/knightslanding/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/mapfile.csv (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemep/ head/lib/libpmcstat/pmu-events/arch/x86/nehalemep/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemep/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemep/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemep/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemep/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemep/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemep/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemex/ head/lib/libpmcstat/pmu-events/arch/x86/nehalemex/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemex/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemex/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemex/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemex/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemex/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/nehalemex/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/sandybridge/ head/lib/libpmcstat/pmu-events/arch/x86/sandybridge/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/sandybridge/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/sandybridge/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/sandybridge/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/sandybridge/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/sandybridge/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/sandybridge/snb-metrics.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/sandybridge/uncore.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/sandybridge/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/silvermont/ head/lib/libpmcstat/pmu-events/arch/x86/silvermont/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/silvermont/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/silvermont/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/silvermont/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/silvermont/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylake/ head/lib/libpmcstat/pmu-events/arch/x86/skylake/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylake/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylake/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylake/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylake/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylake/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylake/skl-metrics.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylake/uncore.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylake/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylakex/ head/lib/libpmcstat/pmu-events/arch/x86/skylakex/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylakex/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylakex/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylakex/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylakex/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylakex/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylakex/skx-metrics.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylakex/uncore-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylakex/uncore-other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/skylakex/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/ head/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/ head/lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereex/ head/lib/libpmcstat/pmu-events/arch/x86/westmereex/cache.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereex/floating-point.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereex/frontend.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereex/memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereex/other.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereex/pipeline.json (contents, props changed) head/lib/libpmcstat/pmu-events/arch/x86/westmereex/virtual-memory.json (contents, props changed) head/lib/libpmcstat/pmu-events/jevents.c (contents, props changed) head/lib/libpmcstat/pmu-events/jevents.h (contents, props changed) head/lib/libpmcstat/pmu-events/jsmn.c (contents, props changed) head/lib/libpmcstat/pmu-events/jsmn.h (contents, props changed) head/lib/libpmcstat/pmu-events/json.c (contents, props changed) head/lib/libpmcstat/pmu-events/json.h (contents, props changed) head/lib/libpmcstat/pmu-events/list.h (contents, props changed) head/lib/libpmcstat/pmu-events/pmu-events.h (contents, props changed) Modified: head/Makefile head/Makefile.inc1 head/lib/libpmcstat/Makefile head/lib/libpmcstat/libpmcstat.h head/sys/amd64/conf/GENERIC-NODEBUG head/usr.sbin/pmcstat/pmcstat.c head/usr.sbin/pmcstat/pmcstat.h Modified: head/Makefile ============================================================================== --- head/Makefile Thu May 24 03:44:12 2018 (r334127) +++ head/Makefile Thu May 24 04:30:06 2018 (r334128) @@ -481,7 +481,8 @@ worlds: .PHONY # existing system is. # .if make(universe) || make(universe_kernels) || make(tinderbox) || make(targets) -TARGETS?=amd64 arm arm64 i386 mips powerpc riscv sparc64 +TARGETS?=amd64 i386 powerpc arm64 +#riscv arm sparc64 mips _UNIVERSE_TARGETS= ${TARGETS} TARGET_ARCHES_arm?= arm armeb armv6 armv7 TARGET_ARCHES_arm64?= aarch64 Modified: head/Makefile.inc1 ============================================================================== --- head/Makefile.inc1 Thu May 24 03:44:12 2018 (r334127) +++ head/Makefile.inc1 Thu May 24 04:30:06 2018 (r334128) @@ -2029,6 +2029,11 @@ _tcsh=bin/csh _libmagic=lib/libmagic .endif +.if (${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" || \ + ${MACHINE_CPUARCH} == "powerpc") +_jevents=lib/libpmcstat/pmu-events +.endif + # kernel-toolchain skips _cleanobj, so handle cleaning up previous # build-tools directories if needed. .if !defined(NO_CLEAN) && make(kernel-toolchain) @@ -2039,6 +2044,7 @@ _bt_clean= ${CLEANDIR} ${_tcsh} \ bin/sh \ ${LOCAL_TOOL_DIRS} \ + ${_jevents} \ lib/ncurses/ncurses \ lib/ncurses/ncursesw \ ${_rescue} \ Modified: head/lib/libpmcstat/Makefile ============================================================================== --- head/lib/libpmcstat/Makefile Thu May 24 03:44:12 2018 (r334127) +++ head/lib/libpmcstat/Makefile Thu May 24 04:30:06 2018 (r334128) @@ -1,5 +1,4 @@ # $FreeBSD$ - PACKAGE=lib${LIB} LIB= pmcstat INTERNALLIB= @@ -10,7 +9,31 @@ SRCS= \ libpmcstat_logging.c \ libpmcstat_process.c \ libpmcstat_string.c \ - libpmcstat_symbol.c + libpmcstat_symbol.c \ + libpmcstat_pmu_util.c INCS= libpmcstat.h + +CFLAGS+= -I${.CURDIR} + +.if (${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" || \ + ${MACHINE_CPUARCH} == "powerpc") +.if ${MACHINE_CPUARCH} == "aarch64" +EVENT_ARCH="arm64" +.elif ${MACHINE_CPUARCH} == "amd64" +EVENT_ARCH="x86" +.elif ${MACHINE_CPUARCH} == "powerpc" +EVENT_ARCH="powerpc" +.endif + +.if defined(HOST_OBJTOP) +JEVENTS= ${HOST_OBJTOP}/${RELDIR}/pmu-events/jevents +.else +JEVENTS= pmu-events/jevents +.endif + +libpmcstat_events.c: ${JEVENTS} + ${JEVENTS} ${EVENT_ARCH} ${.CURDIR}/pmu-events/arch libpmcstat_events.c +SRCS+= libpmcstat_events.c +.endif .include <bsd.lib.mk> Modified: head/lib/libpmcstat/libpmcstat.h ============================================================================== --- head/lib/libpmcstat/libpmcstat.h Thu May 24 03:44:12 2018 (r334127) +++ head/lib/libpmcstat/libpmcstat.h Thu May 24 04:30:06 2018 (r334128) @@ -53,6 +53,7 @@ #define PMCSTAT_NHASH 256 #define PMCSTAT_HASH_MASK 0xFF +#define DEFAULT_SAMPLE_COUNT 65536 typedef const void *pmcstat_interned_string; struct pmc_plugins; @@ -380,6 +381,9 @@ int pmcstat_analyze_log(struct pmcstat_args *args, int pmcstat_open_log(const char *_p, int _mode); int pmcstat_close_log(struct pmcstat_args *args); + +uint64_t pmcstat_pmu_sample_rate_get(const char *); + __END_DECLS #endif /* !_LIBPMCSTAT_H_ */ Added: head/lib/libpmcstat/libpmcstat_pmu_util.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/lib/libpmcstat/libpmcstat_pmu_util.c Thu May 24 04:30:06 2018 (r334128) @@ -0,0 +1,128 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018, Matthew Macy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + * + */ + +#include <sys/types.h> +#include <sys/errno.h> +#include <sys/sysctl.h> +#include <stddef.h> +#include <stdlib.h> +#include <limits.h> +#include <string.h> +#include <pmc.h> +#include <pmclog.h> +#include <libpmcstat.h> +#include "pmu-events/pmu-events.h" + +#if defined(__amd64__) +struct pmu_event_desc { + uint32_t ped_umask; + uint32_t ped_event; + uint64_t ped_period; +}; + +static const struct pmu_events_map * +pmu_events_map_get(void) +{ + size_t s; + char buf[64]; + const struct pmu_events_map *pme; + + if (sysctlbyname("kern.hwpmc.cpuid", (void *)NULL, &s, + (void *)NULL, 0) == -1) + return (NULL); + if (sysctlbyname("kern.hwpmc.cpuid", buf, &s, + (void *)NULL, 0) == -1) + return (NULL); + for (pme = pmu_events_map; pme->cpuid != NULL; pme++) + if (strcmp(buf, pme->cpuid) == 0) + return (pme); + return (NULL); +} + +static const struct pmu_event * +pmu_event_get(const char *event_name) +{ + const struct pmu_events_map *pme; + const struct pmu_event *pe; + + if ((pme = pmu_events_map_get()) == NULL) + return (NULL); + for (pe = pme->table; pe->name != NULL; pe++) + if (strcmp(pe->name, event_name) == 0) + return (pe); + return (NULL); +} + +static int +pmu_parse_event(struct pmu_event_desc *ped, const char *eventin) +{ + char *event; + char *kvp, *key, *value; + + if ((event = strdup(eventin)) == NULL) + return (ENOMEM); + bzero(ped, sizeof(*ped)); + while ((kvp = strsep(&event, ",")) != NULL) { + key = strsep(&kvp, "="); + if (key == NULL) + abort(); + value = kvp; + if (strcmp(key, "umask") == 0) + ped->ped_umask = strtol(value, NULL, 16); + if (strcmp(key, "event") == 0) + ped->ped_event = strtol(value, NULL, 16); + if (strcmp(key, "period") == 0) + ped->ped_umask = strtol(value, NULL, 10); + } + free(event); + return (0); +} + +uint64_t +pmcstat_pmu_sample_rate_get(const char *event_name) +{ + const struct pmu_event *pe; + struct pmu_event_desc ped; + + if ((pe = pmu_event_get(event_name)) == NULL) + return (DEFAULT_SAMPLE_COUNT); + if (pe->alias && (pe = pmu_event_get(pe->alias)) == NULL) + return (DEFAULT_SAMPLE_COUNT); + if (pe->event == NULL) + return (DEFAULT_SAMPLE_COUNT); + if (pmu_parse_event(&ped, pe->event)) + return (DEFAULT_SAMPLE_COUNT); + return (ped.ped_period); +} + +#else +uint64_t pmcstat_pmu_sample_rate_get(void) { return (DEFAULT_SAMPLE_COUNT); } +#endif Added: head/lib/libpmcstat/pmu-events/Makefile ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/lib/libpmcstat/pmu-events/Makefile Thu May 24 04:30:06 2018 (r334128) @@ -0,0 +1,9 @@ +# $FreeBSD$ + +PROG=jevents +SRCS=jevents.c jsmn.c json.c +CFLAGS+= -Wno-cast-qual +.PATH: ${.CURDIR} +build-tools: jevents +MAN= +.include <bsd.prog.mk> Added: head/lib/libpmcstat/pmu-events/README ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/lib/libpmcstat/pmu-events/README Thu May 24 04:30:06 2018 (r334128) @@ -0,0 +1,152 @@ + +The contents of this directory allow users to specify PMU events in their +CPUs by their symbolic names rather than raw event codes (see example below). + +The main program in this directory, is the 'jevents', which is built and +executed _BEFORE_ the perf binary itself is built. + +The 'jevents' program tries to locate and process JSON files in the directory +tree tools/perf/pmu-events/arch/foo. + + - Regular files with '.json' extension in the name are assumed to be + JSON files, each of which describes a set of PMU events. + + - The CSV file that maps a specific CPU to its set of PMU events is to + be named 'mapfile.csv' (see below for mapfile format). + + - Directories are traversed, but all other files are ignored. + + - To reduce JSON event duplication per architecture, platform JSONs may + use "ArchStdEvent" keyword to dereference an "Architecture standard + events", defined in architecture standard JSONs. + Architecture standard JSONs must be located in the architecture root + folder. Matching is based on the "EventName" field. + +The PMU events supported by a CPU model are expected to grouped into topics +such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic +should be placed in a separate JSON file - where the file name identifies +the topic. Eg: "Floating-point.json". + +All the topic JSON files for a CPU model/family should be in a separate +sub directory. Thus for the Silvermont X86 CPU: + + $ ls tools/perf/pmu-events/arch/x86/Silvermont_core + Cache.json Memory.json Virtual-Memory.json + Frontend.json Pipeline.json + +The JSONs folder for a CPU model/family may be placed in the root arch +folder, or may be placed in a vendor sub-folder under the arch folder +for instances where the arch and vendor are not the same. + +Using the JSON files and the mapfile, 'jevents' generates the C source file, +'pmu-events.c', which encodes the two sets of tables: + + - Set of 'PMU events tables' for all known CPUs in the architecture, + (one table like the following, per JSON file; table name 'pme_power8' + is derived from JSON file name, 'power8.json'). + + struct pmu_event pme_power8[] = { + + ... + + { + .name = "pm_1plus_ppc_cmpl", + .event = "event=0x100f2", + .desc = "1 or more ppc insts finished,", + }, + + ... + } + + - A 'mapping table' that maps each CPU of the architecture, to its + 'PMU events table' + + struct pmu_events_map pmu_events_map[] = { + { + .cpuid = "004b0000", + .version = "1", + .type = "core", + .table = pme_power8 + }, + ... + + }; + +After the 'pmu-events.c' is generated, it is compiled and the resulting +'pmu-events.o' is added to 'libperf.a' which is then used to build perf. + +NOTES: + 1. Several CPUs can support same set of events and hence use a common + JSON file. Hence several entries in the pmu_events_map[] could map + to a single 'PMU events table'. + + 2. The 'pmu-events.h' has an extern declaration for the mapping table + and the generated 'pmu-events.c' defines this table. + + 3. _All_ known CPU tables for architecture are included in the perf + binary. + +At run time, perf determines the actual CPU it is running on, finds the +matching events table and builds aliases for those events. This allows +users to specify events by their name: + + $ perf stat -e pm_1plus_ppc_cmpl sleep 1 + +where 'pm_1plus_ppc_cmpl' is a Power8 PMU event. + +However some errors in processing may cause the perf build to fail. + +Mapfile format +=============== + +The mapfile enables multiple CPU models to share a single set of PMU events. +It is required even if such mapping is 1:1. + +The mapfile.csv format is expected to be: + + Header line + CPUID,Version,Dir/path/name,Type + +where: + + Comma: + is the required field delimiter (i.e other fields cannot + have commas within them). + + Comments: + Lines in which the first character is either '\n' or '#' + are ignored. + + Header line + The header line is the first line in the file, which is + always _IGNORED_. It can empty. + + CPUID: + CPUID is an arch-specific char string, that can be used + to identify CPU (and associate it with a set of PMU events + it supports). Multiple CPUIDS can point to the same + File/path/name.json. + + Example: + CPUID == 'GenuineIntel-6-2E' (on x86). + CPUID == '004b0100' (PVR value in Powerpc) + Version: + is the Version of the mapfile. + + Dir/path/name: + is the pathname to the directory containing the CPU's JSON + files, relative to the directory containing the mapfile.csv + + Type: + indicates whether the events or "core" or "uncore" events. + + + Eg: + + $ grep Silvermont tools/perf/pmu-events/arch/x86/mapfile.csv + GenuineIntel-6-37,V13,Silvermont_core,core + GenuineIntel-6-4D,V13,Silvermont_core,core + GenuineIntel-6-4C,V13,Silvermont_core,core + + i.e the three CPU models use the JSON files (i.e PMU events) listed + in the directory 'tools/perf/pmu-events/arch/x86/Silvermont_core'. Added: head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/branch.json ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/branch.json Thu May 24 04:30:06 2018 (r334128) @@ -0,0 +1,25 @@ +[ + { + "ArchStdEvent": "BR_INDIRECT_SPEC", + }, + { + "EventCode": "0xC9", + "EventName": "BR_COND", + "BriefDescription": "Conditional branch executed" + }, + { + "EventCode": "0xCA", + "EventName": "BR_INDIRECT_MISPRED", + "BriefDescription": "Indirect branch mispredicted" + }, + { + "EventCode": "0xCB", + "EventName": "BR_INDIRECT_MISPRED_ADDR", + "BriefDescription": "Indirect branch mispredicted because of address miscompare" + }, + { + "EventCode": "0xCC", + "EventName": "BR_COND_MISPRED", + "BriefDescription": "Conditional branch mispredicted" + } +] Added: head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/bus.json ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/bus.json Thu May 24 04:30:06 2018 (r334128) @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "BUS_ACCESS_RD", + }, + { + "ArchStdEvent": "BUS_ACCESS_WR", + } +] Added: head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/cache.json ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/cache.json Thu May 24 04:30:06 2018 (r334128) @@ -0,0 +1,27 @@ +[ + { + "EventCode": "0xC2", + "EventName": "PREFETCH_LINEFILL", + "BriefDescription": "Linefill because of prefetch" + }, + { + "EventCode": "0xC3", + "EventName": "PREFETCH_LINEFILL_DROP", + "BriefDescription": "Instruction Cache Throttle occurred" + }, + { + "EventCode": "0xC4", + "EventName": "READ_ALLOC_ENTER", + "BriefDescription": "Entering read allocate mode" + }, + { + "EventCode": "0xC5", + "EventName": "READ_ALLOC", + "BriefDescription": "Read allocate mode" + }, + { + "EventCode": "0xC8", + "EventName": "EXT_SNOOP", + "BriefDescription": "SCU Snooped data from another CPU for this CPU" + } +] Added: head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/memory.json ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/memory.json Thu May 24 04:30:06 2018 (r334128) @@ -0,0 +1,12 @@ +[ + { + "EventCode": "0xC0", + "EventName": "EXT_MEM_REQ", + "BriefDescription": "External memory request" + }, + { + "EventCode": "0xC1", + "EventName": "EXT_MEM_REQ_NC", + "BriefDescription": "Non-cacheable external memory request" + } +] Added: head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/other.json ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/other.json Thu May 24 04:30:06 2018 (r334128) @@ -0,0 +1,28 @@ +[ + { + "ArchStdEvent": "EXC_IRQ", + }, + { + "ArchStdEvent": "EXC_FIQ", + }, + { + "EventCode": "0xC6", + "EventName": "PRE_DECODE_ERR", + "BriefDescription": "Pre-decode error" + }, + { + "EventCode": "0xD0", + "EventName": "L1I_CACHE_ERR", + "BriefDescription": "L1 Instruction Cache (data or tag) memory error" + }, + { + "EventCode": "0xD1", + "EventName": "L1D_CACHE_ERR", + "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" + }, + { + "EventCode": "0xD2", + "EventName": "TLB_ERR", + "BriefDescription": "TLB memory error" + } +] Added: head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json Thu May 24 04:30:06 2018 (r334128) @@ -0,0 +1,52 @@ +[ + { + "EventCode": "0xC7", + "EventName": "STALL_SB_FULL", + "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full" + }, + { + "EventCode": "0xE0", + "EventName": "OTHER_IQ_DEP_STALL", + "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error" + }, + { + "EventCode": "0xE1", + "EventName": "IC_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed" + }, + { + "EventCode": "0xE2", + "EventName": "IUTLB_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed" + }, + { + "EventCode": "0xE3", + "EventName": "DECODE_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" + }, + { + "EventCode": "0xE4", + "EventName": "OTHER_INTERLOCK_STALL", + "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction" + }, + { + "EventCode": "0xE5", + "EventName": "AGU_DEP_STALL", + "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU" + }, + { + "EventCode": "0xE6", + "EventName": "SIMD_DEP_STALL", + "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." + }, + { + "EventCode": "0xE7", + "EventName": "LD_DEP_STALL", + "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" + }, + { + "EventCode": "0xE8", + "EventName": "ST_DEP_STALL", + "BriefDescription": "Cycles there is a stall in the Wr stage because of a store" + } +] Added: head/lib/libpmcstat/pmu-events/arch/arm64/armv8-recommended.json ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/lib/libpmcstat/pmu-events/arch/arm64/armv8-recommended.json Thu May 24 04:30:06 2018 (r334128) @@ -0,0 +1,452 @@ +[ + { + "PublicDescription": "Attributable Level 1 data cache access, read", + "EventCode": "0x40", + "EventName": "L1D_CACHE_RD", + "BriefDescription": "L1D cache access, read" + }, + { + "PublicDescription": "Attributable Level 1 data cache access, write", + "EventCode": "0x41", + "EventName": "L1D_CACHE_WR", + "BriefDescription": "L1D cache access, write" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, read", + "EventCode": "0x42", + "EventName": "L1D_CACHE_REFILL_RD", + "BriefDescription": "L1D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, write", + "EventCode": "0x43", + "EventName": "L1D_CACHE_REFILL_WR", + "BriefDescription": "L1D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, inner", + "EventCode": "0x44", + "EventName": "L1D_CACHE_REFILL_INNER", + "BriefDescription": "L1D cache refill, inner" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, outer", + "EventCode": "0x45", + "EventName": "L1D_CACHE_REFILL_OUTER", + "BriefDescription": "L1D cache refill, outer" + }, + { + "PublicDescription": "Attributable Level 1 data cache Write-Back, victim", + "EventCode": "0x46", + "EventName": "L1D_CACHE_WB_VICTIM", + "BriefDescription": "L1D cache Write-Back, victim" + }, + { + "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency", + "EventCode": "0x47", + "EventName": "L1D_CACHE_WB_CLEAN", + "BriefDescription": "L1D cache Write-Back, cleaning and coherency" + }, + { + "PublicDescription": "Attributable Level 1 data cache invalidate", + "EventCode": "0x48", + "EventName": "L1D_CACHE_INVAL", + "BriefDescription": "L1D cache invalidate" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, read", + "EventCode": "0x4C", + "EventName": "L1D_TLB_REFILL_RD", + "BriefDescription": "L1D tlb refill, read" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, write", + "EventCode": "0x4D", + "EventName": "L1D_TLB_REFILL_WR", + "BriefDescription": "L1D tlb refill, write" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, read", + "EventCode": "0x4E", + "EventName": "L1D_TLB_RD", + "BriefDescription": "L1D tlb access, read" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, write", + "EventCode": "0x4F", + "EventName": "L1D_TLB_WR", + "BriefDescription": "L1D tlb access, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache access, read", + "EventCode": "0x50", + "EventName": "L2D_CACHE_RD", + "BriefDescription": "L2D cache access, read" + }, + { + "PublicDescription": "Attributable Level 2 data cache access, write", + "EventCode": "0x51", + "EventName": "L2D_CACHE_WR", + "BriefDescription": "L2D cache access, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache refill, read", + "EventCode": "0x52", + "EventName": "L2D_CACHE_REFILL_RD", + "BriefDescription": "L2D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 2 data cache refill, write", + "EventCode": "0x53", + "EventName": "L2D_CACHE_REFILL_WR", + "BriefDescription": "L2D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache Write-Back, victim", + "EventCode": "0x56", + "EventName": "L2D_CACHE_WB_VICTIM", + "BriefDescription": "L2D cache Write-Back, victim" + }, + { + "PublicDescription": "Level 2 data cache Write-Back, cleaning and coherency", + "EventCode": "0x57", + "EventName": "L2D_CACHE_WB_CLEAN", + "BriefDescription": "L2D cache Write-Back, cleaning and coherency" + }, + { + "PublicDescription": "Attributable Level 2 data cache invalidate", + "EventCode": "0x58", + "EventName": "L2D_CACHE_INVAL", + "BriefDescription": "L2D cache invalidate" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB refill, read", + "EventCode": "0x5c", + "EventName": "L2D_TLB_REFILL_RD", + "BriefDescription": "L2D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB refill, write", + "EventCode": "0x5d", + "EventName": "L2D_TLB_REFILL_WR", + "BriefDescription": "L2D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB access, read", + "EventCode": "0x5e", + "EventName": "L2D_TLB_RD", + "BriefDescription": "L2D cache access, read" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB access, write", + "EventCode": "0x5f", + "EventName": "L2D_TLB_WR", + "BriefDescription": "L2D cache access, write" + }, + { + "PublicDescription": "Bus access read", + "EventCode": "0x60", + "EventName": "BUS_ACCESS_RD", + "BriefDescription": "Bus access read" + }, + { + "PublicDescription": "Bus access write", + "EventCode": "0x61", + "EventName": "BUS_ACCESS_WR", + "BriefDescription": "Bus access write" + } + { + "PublicDescription": "Bus access, Normal, Cacheable, Shareable", + "EventCode": "0x62", + "EventName": "BUS_ACCESS_SHARED", + "BriefDescription": "Bus access, Normal, Cacheable, Shareable" + } + { + "PublicDescription": "Bus access, not Normal, Cacheable, Shareable", + "EventCode": "0x63", + "EventName": "BUS_ACCESS_NOT_SHARED", + "BriefDescription": "Bus access, not Normal, Cacheable, Shareable" + } + { + "PublicDescription": "Bus access, Normal", + "EventCode": "0x64", + "EventName": "BUS_ACCESS_NORMAL", + "BriefDescription": "Bus access, Normal" + } + { + "PublicDescription": "Bus access, peripheral", + "EventCode": "0x65", + "EventName": "BUS_ACCESS_PERIPH", + "BriefDescription": "Bus access, peripheral" + } + { + "PublicDescription": "Data memory access, read", + "EventCode": "0x66", + "EventName": "MEM_ACCESS_RD", + "BriefDescription": "Data memory access, read" + } + { + "PublicDescription": "Data memory access, write", + "EventCode": "0x67", + "EventName": "MEM_ACCESS_WR", + "BriefDescription": "Data memory access, write" + } + { + "PublicDescription": "Unaligned access, read", + "EventCode": "0x68", + "EventName": "UNALIGNED_LD_SPEC", + "BriefDescription": "Unaligned access, read" + } + { + "PublicDescription": "Unaligned access, write", + "EventCode": "0x69", + "EventName": "UNALIGNED_ST_SPEC", + "BriefDescription": "Unaligned access, write" + } + { + "PublicDescription": "Unaligned access", + "EventCode": "0x6a", + "EventName": "UNALIGNED_LDST_SPEC", + "BriefDescription": "Unaligned access" + } + { + "PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX", + "EventCode": "0x6c", + "EventName": "LDREX_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass", + "EventCode": "0x6d", + "EventName": "STREX_PASS_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail", + "EventCode": "0x6e", + "EventName": "STREX_FAIL_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX", + "EventCode": "0x6f", + "EventName": "STREX_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX" + } + { + "PublicDescription": "Operation speculatively executed, load", + "EventCode": "0x70", + "EventName": "LD_SPEC", + "BriefDescription": "Operation speculatively executed, load" + } + { + "PublicDescription": "Operation speculatively executed, store" + "EventCode": "0x71", + "EventName": "ST_SPEC", + "BriefDescription": "Operation speculatively executed, store" + } + { + "PublicDescription": "Operation speculatively executed, load or store", + "EventCode": "0x72", + "EventName": "LDST_SPEC", + "BriefDescription": "Operation speculatively executed, load or store" + } + { + "PublicDescription": "Operation speculatively executed, integer data processing", + "EventCode": "0x73", + "EventName": "DP_SPEC", + "BriefDescription": "Operation speculatively executed, integer data processing" + } + { + "PublicDescription": "Operation speculatively executed, Advanced SIMD instruction", + "EventCode": "0x74", + "EventName": "ASE_SPEC", + "BriefDescription": "Operation speculatively executed, Advanced SIMD instruction", + } + { + "PublicDescription": "Operation speculatively executed, floating-point instruction", + "EventCode": "0x75", + "EventName": "VFP_SPEC", + "BriefDescription": "Operation speculatively executed, floating-point instruction" + } + { + "PublicDescription": "Operation speculatively executed, software change of the PC", + "EventCode": "0x76", + "EventName": "PC_WRITE_SPEC", + "BriefDescription": "Operation speculatively executed, software change of the PC" + } + { + "PublicDescription": "Operation speculatively executed, Cryptographic instruction", + "EventCode": "0x77", + "EventName": "CRYPTO_SPEC", + "BriefDescription": "Operation speculatively executed, Cryptographic instruction" + } + { + "PublicDescription": "Branch speculatively executed, immediate branch" + "EventCode": "0x78", + "EventName": "BR_IMMED_SPEC", + "BriefDescription": "Branch speculatively executed, immediate branch" + } + { + "PublicDescription": "Branch speculatively executed, procedure return" + "EventCode": "0x79", + "EventName": "BR_RETURN_SPEC", + "BriefDescription": "Branch speculatively executed, procedure return" + } + { + "PublicDescription": "Branch speculatively executed, indirect branch" + "EventCode": "0x7a", + "EventName": "BR_INDIRECT_SPEC", + "BriefDescription": "Branch speculatively executed, indirect branch" + } + { + "PublicDescription": "Barrier speculatively executed, ISB" + "EventCode": "0x7c", + "EventName": "ISB_SPEC", + "BriefDescription": "Barrier speculatively executed, ISB" + } + { + "PublicDescription": "Barrier speculatively executed, DSB" + "EventCode": "0x7d", + "EventName": "DSB_SPEC", + "BriefDescription": "Barrier speculatively executed, DSB" + } + { + "PublicDescription": "Barrier speculatively executed, DMB" + "EventCode": "0x7e", + "EventName": "DMB_SPEC", + "BriefDescription": "Barrier speculatively executed, DMB" + } + { + "PublicDescription": "Exception taken, Other synchronous" + "EventCode": "0x81", + "EventName": "EXC_UNDEF", + "BriefDescription": "Exception taken, Other synchronous" + } + { + "PublicDescription": "Exception taken, Supervisor Call" + "EventCode": "0x82", + "EventName": "EXC_SVC", + "BriefDescription": "Exception taken, Supervisor Call" + } + { + "PublicDescription": "Exception taken, Instruction Abort" + "EventCode": "0x83", + "EventName": "EXC_PABORT", + "BriefDescription": "Exception taken, Instruction Abort" + } + { + "PublicDescription": "Exception taken, Data Abort and SError" + "EventCode": "0x84", + "EventName": "EXC_DABORT", + "BriefDescription": "Exception taken, Data Abort and SError" + } + { + "PublicDescription": "Exception taken, IRQ" + "EventCode": "0x86", + "EventName": "EXC_IRQ", + "BriefDescription": "Exception taken, IRQ" + } + { + "PublicDescription": "Exception taken, FIQ" + "EventCode": "0x87", + "EventName": "EXC_FIQ", + "BriefDescription": "Exception taken, FIQ" + } + { + "PublicDescription": "Exception taken, Secure Monitor Call" + "EventCode": "0x88", + "EventName": "EXC_SMC", + "BriefDescription": "Exception taken, Secure Monitor Call" + } + { + "PublicDescription": "Exception taken, Hypervisor Call" + "EventCode": "0x8a", + "EventName": "EXC_HVC", + "BriefDescription": "Exception taken, Hypervisor Call" + } + { + "PublicDescription": "Exception taken, Instruction Abort not taken locally" + "EventCode": "0x8b", + "EventName": "EXC_TRAP_PABORT", + "BriefDescription": "Exception taken, Instruction Abort not taken locally" + } + { + "PublicDescription": "Exception taken, Data Abort or SError not taken locally" + "EventCode": "0x8c", + "EventName": "EXC_TRAP_DABORT", + "BriefDescription": "Exception taken, Data Abort or SError not taken locally" + } + { + "PublicDescription": "Exception taken, Other traps not taken locally" + "EventCode": "0x8d", + "EventName": "EXC_TRAP_OTHER", + "BriefDescription": "Exception taken, Other traps not taken locally" + } + { + "PublicDescription": "Exception taken, IRQ not taken locally" + "EventCode": "0x8e", + "EventName": "EXC_TRAP_IRQ", + "BriefDescription": "Exception taken, IRQ not taken locally" + } + { + "PublicDescription": "Exception taken, FIQ not taken locally" + "EventCode": "0x8f", + "EventName": "EXC_TRAP_FIQ", + "BriefDescription": "Exception taken, FIQ not taken locally" + } + { + "PublicDescription": "Release consistency operation speculatively executed, Load-Acquire" + "EventCode": "0x90", + "EventName": "RC_LD_SPEC", + "BriefDescription": "Release consistency operation speculatively executed, Load-Acquire" + } + { + "PublicDescription": "Release consistency operation speculatively executed, Store-Release" + "EventCode": "0x91", + "EventName": "RC_ST_SPEC", + "BriefDescription": "Release consistency operation speculatively executed, Store-Release" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, read" + "EventCode": "0xa0", + "EventName": "L3D_CACHE_RD", + "BriefDescription": "Attributable Level 3 data or unified cache access, read" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, write" + "EventCode": "0xa1", + "EventName": "L3D_CACHE_WR", + "BriefDescription": "Attributable Level 3 data or unified cache access, write" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache refill, read" + "EventCode": "0xa2", + "EventName": "L3D_CACHE_REFILL_RD", + "BriefDescription": "Attributable Level 3 data or unified cache refill, read" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache refill, write" + "EventCode": "0xa3", + "EventName": "L3D_CACHE_REFILL_WR", + "BriefDescription": "Attributable Level 3 data or unified cache refill, write" + } + { *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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