Date: Fri, 20 Dec 2013 00:56:24 +0000 (UTC) From: Ganbold Tsagaankhuu <ganbold@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r259640 - in head/sys: arm/arm arm/include conf Message-ID: <201312200056.rBK0uO2H091437@svn.freebsd.org>
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Author: ganbold (doc committer) Date: Fri Dec 20 00:56:23 2013 New Revision: 259640 URL: http://svnweb.freebsd.org/changeset/base/259640 Log: Add identification and necessary type checks for Krait CPU cores. Krait CPU is used in Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064. Approved by: stas (mentor) Modified: head/sys/arm/arm/cpufunc.c head/sys/arm/arm/elf_trampoline.c head/sys/arm/arm/identcpu.c head/sys/arm/arm/locore.S head/sys/arm/arm/swtch.S head/sys/arm/include/armreg.h head/sys/arm/include/cpuconf.h head/sys/arm/include/cpufunc.h head/sys/arm/include/intr.h head/sys/arm/include/md_var.h head/sys/conf/files.arm head/sys/conf/options.arm Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/arm/arm/cpufunc.c Fri Dec 20 00:56:23 2013 (r259640) @@ -1038,7 +1038,7 @@ struct cpu_functions arm1176_cpufuncs = }; #endif /*CPU_ARM1176 */ -#if defined(CPU_CORTEXA) +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) struct cpu_functions cortexa_cpufuncs = { /* CPU functions */ @@ -1118,7 +1118,7 @@ u_int cpu_reset_needs_v4_MMU_disable; /* defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_FA526) || defined(CPU_FA626TE) || defined(CPU_MV_PJ4B) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ - defined(CPU_CORTEXA) + defined(CPU_CORTEXA) || defined(CPU_KRAIT) static void get_cachetype_cp15(void); @@ -1416,7 +1416,7 @@ set_cpufuncs() goto out; } #endif /* CPU_ARM1136 || CPU_ARM1176 */ -#ifdef CPU_CORTEXA +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) if (cputype == CPU_ID_CORTEXA5 || cputype == CPU_ID_CORTEXA7 || cputype == CPU_ID_CORTEXA8R1 || @@ -1425,7 +1425,8 @@ set_cpufuncs() cputype == CPU_ID_CORTEXA9R1 || cputype == CPU_ID_CORTEXA9R2 || cputype == CPU_ID_CORTEXA9R3 || - cputype == CPU_ID_CORTEXA15 ) { + cputype == CPU_ID_CORTEXA15 || + cputype == CPU_ID_KRAIT ) { cpufuncs = cortexa_cpufuncs; cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ get_cachetype_cp15(); @@ -2407,7 +2408,7 @@ pj4bv7_setup(args) } #endif /* CPU_MV_PJ4B */ -#ifdef CPU_CORTEXA +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) void cortexa_setup(char *args) Modified: head/sys/arm/arm/elf_trampoline.c ============================================================================== --- head/sys/arm/arm/elf_trampoline.c Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/arm/arm/elf_trampoline.c Fri Dec 20 00:56:23 2013 (r259640) @@ -102,7 +102,7 @@ extern void xscalec3_l2cache_purge(void) #elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) #define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all extern void sheeva_l2cache_wbinv_all(void); -#elif defined(CPU_CORTEXA) +#elif defined(CPU_CORTEXA) || defined(CPU_KRAIT) #define cpu_idcache_wbinv_all armv7_idcache_wbinv_all #define cpu_l2cache_wbinv_all() #else Modified: head/sys/arm/arm/identcpu.c ============================================================================== --- head/sys/arm/arm/identcpu.c Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/arm/arm/identcpu.c Fri Dec 20 00:56:23 2013 (r259640) @@ -254,6 +254,8 @@ const struct cpuidtab cpuids[] = { generic_steppings }, { CPU_ID_CORTEXA15, CPU_CLASS_CORTEXA, "Cortex A15", generic_steppings }, + { CPU_ID_KRAIT, CPU_CLASS_KRAIT, "Krait", + generic_steppings }, { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", sa110_steppings }, @@ -353,6 +355,7 @@ const struct cpu_classtab cpu_classes[] { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ { "Cortex-A", "CPU_CORTEXA" }, /* CPU_CLASS_CORTEXA */ + { "Krait", "CPU_KRAIT" }, /* CPU_CLASS_KRAIT */ { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ Modified: head/sys/arm/arm/locore.S ============================================================================== --- head/sys/arm/arm/locore.S Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/arm/arm/locore.S Fri Dec 20 00:56:23 2013 (r259640) @@ -170,7 +170,7 @@ Lunmapped: mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ -#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ #endif @@ -377,7 +377,7 @@ Ltag: mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ -#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ #endif @@ -389,7 +389,7 @@ Ltag: mcr p15, 0, r0, c3, c0, 0 /* Enable MMU */ mrc p15, 0, r0, c1, c0, 0 -#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) orr r0, r0, #CPU_CONTROL_V6_EXTPAGE orr r0, r0, #CPU_CONTROL_AF_ENABLE #endif Modified: head/sys/arm/arm/swtch.S ============================================================================== --- head/sys/arm/arm/swtch.S Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/arm/arm/swtch.S Fri Dec 20 00:56:23 2013 (r259640) @@ -131,7 +131,7 @@ ENTRY(cpu_throw) /* Switch to lwp0 context */ ldr r9, .Lcpufuncs -#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) +#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) && !defined(CPU_KRAIT) mov lr, pc ldr pc, [r9, #CF_IDCACHE_WBINV_ALL] #endif @@ -361,7 +361,7 @@ ENTRY(cpu_switch) cmpeq r0, r5 /* Same DACR? */ beq .Lcs_context_switched /* yes! */ -#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) +#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) && !defined(CPU_KRAIT) /* * Definately need to flush the cache. */ Modified: head/sys/arm/include/armreg.h ============================================================================== --- head/sys/arm/include/armreg.h Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/arm/include/armreg.h Fri Dec 20 00:56:23 2013 (r259640) @@ -158,6 +158,7 @@ #define CPU_ID_CORTEXA15 0x410fc0f0 #define CPU_ID_SA110 0x4401a100 #define CPU_ID_SA1100 0x4401a110 +#define CPU_ID_KRAIT 0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */ #define CPU_ID_TI925T 0x54029250 #define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ #define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ Modified: head/sys/arm/include/cpuconf.h ============================================================================== --- head/sys/arm/include/cpuconf.h Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/arm/include/cpuconf.h Fri Dec 20 00:56:23 2013 (r259640) @@ -66,6 +66,7 @@ defined(CPU_FA626TE) + \ defined(CPU_XSCALE_IXP425)) + \ defined(CPU_CORTEXA) + \ + defined(CPU_KRAIT) + \ defined(CPU_MV_PJ4B) /* @@ -97,7 +98,7 @@ #endif #endif -#if defined(CPU_CORTEXA) +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) #define ARM_ARCH_7A 1 #else #define ARM_ARCH_7A 0 @@ -156,7 +157,7 @@ #define ARM_MMU_V6 0 #endif -#if defined(CPU_CORTEXA) +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) #define ARM_MMU_V7 1 #else #define ARM_MMU_V7 0 Modified: head/sys/arm/include/cpufunc.h ============================================================================== --- head/sys/arm/include/cpufunc.h Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/arm/include/cpufunc.h Fri Dec 20 00:56:23 2013 (r259640) @@ -188,7 +188,7 @@ extern u_int cputype; #else void tlb_broadcast(int); -#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) +#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) #define TLB_BROADCAST /* No need to explicitely send an IPI */ #else #define TLB_BROADCAST tlb_broadcast(7) @@ -463,7 +463,7 @@ void sheeva_l2cache_wbinv_all (void); #endif #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \ - defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) + defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) void arm11_setttb (u_int); void arm11_sleep (int); Modified: head/sys/arm/include/intr.h ============================================================================== --- head/sys/arm/include/intr.h Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/arm/include/intr.h Fri Dec 20 00:56:23 2013 (r259640) @@ -52,6 +52,8 @@ #define NIRQ 64 #elif defined(CPU_CORTEXA) #define NIRQ 160 +#elif defined(CPU_KRAIT) +#define NIRQ 288 #elif defined(CPU_ARM1136) || defined(CPU_ARM1176) #define NIRQ 128 #elif defined(SOC_MV_ARMADAXP) Modified: head/sys/arm/include/md_var.h ============================================================================== --- head/sys/arm/include/md_var.h Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/arm/include/md_var.h Fri Dec 20 00:56:23 2013 (r259640) @@ -63,6 +63,7 @@ enum cpu_class { CPU_CLASS_ARM10E, CPU_CLASS_ARM10EJ, CPU_CLASS_CORTEXA, + CPU_CLASS_KRAIT, CPU_CLASS_SA1, CPU_CLASS_XSCALE, CPU_CLASS_ARM11J, Modified: head/sys/conf/files.arm ============================================================================== --- head/sys/conf/files.arm Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/conf/files.arm Fri Dec 20 00:56:23 2013 (r259640) @@ -6,7 +6,7 @@ arm/arm/blockio.S standard arm/arm/bootconfig.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/busdma_machdep.c optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_sa1100 | cpu_sa1110 | cpu_xscale_80219 | cpu_xscale_80321 | cpu_xscale_81342 | cpu_xscale_ixp425 | cpu_xscale_ixp435 | cpu_xscale_pxa2x0 -arm/arm/busdma_machdep-v6.c optional cpu_arm1136 | cpu_arm1176 | cpu_cortexa | cpu_mv_pj4b +arm/arm/busdma_machdep-v6.c optional cpu_arm1136 | cpu_arm1176 | cpu_cortexa | cpu_mv_pj4b | cpu_krait arm/arm/copystr.S standard arm/arm/cpufunc.c standard arm/arm/cpufunc_asm.S standard @@ -36,7 +36,7 @@ arm/arm/nexus.c standard arm/arm/pl190.c optional pl190 arm/arm/pl310.c optional pl310 arm/arm/pmap.c optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_sa1100 | cpu_sa1110 | cpu_xscale_80219 | cpu_xscale_80321 | cpu_xscale_81342 | cpu_xscale_ixp425 | cpu_xscale_ixp435 | cpu_xscale_pxa2x0 -arm/arm/pmap-v6.c optional cpu_arm1136 | cpu_arm1176 | cpu_cortexa | cpu_mv_pj4b +arm/arm/pmap-v6.c optional cpu_arm1136 | cpu_arm1176 | cpu_cortexa | cpu_mv_pj4b | cpu_krait arm/arm/sc_machdep.c optional sc arm/arm/setcpsr.S standard arm/arm/setstack.s standard Modified: head/sys/conf/options.arm ============================================================================== --- head/sys/conf/options.arm Fri Dec 20 00:47:54 2013 (r259639) +++ head/sys/conf/options.arm Fri Dec 20 00:56:23 2013 (r259640) @@ -12,6 +12,7 @@ CPU_ARM9E opt_global.h CPU_ARM1136 opt_global.h CPU_ARM1176 opt_global.h CPU_CORTEXA opt_global.h +CPU_KRAIT opt_global.h CPU_FA526 opt_global.h CPU_FA626TE opt_global.h CPU_MV_PJ4B opt_global.h
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