Date: Thu, 4 Sep 2008 19:43:14 +0000 (UTC) From: Marius Strobl <marius@FreeBSD.org> To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org Subject: cvs commit: src/sys/sparc64/include tte.h src/sys/sparc64/sparc64 pmap.c Message-ID: <200809041943.m84JhXxf013190@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
marius 2008-09-04 19:43:14 UTC
FreeBSD src repository
Modified files:
sys/sparc64/include tte.h
sys/sparc64/sparc64 pmap.c
Log:
SVN rev 182767 on 2008-09-04 19:43:14Z by marius
The physical address space of cheetah-class CPUs has been extended
to 43 bits so update TD_PA_BITS accordingly. For the most part this
increase is transparent to the existing code except for when reading
the physical address from ASI_{D,I}TLB_DATA_ACCESS_REG, which we
only do in the loader and which was already adjusted in r182478, or
from the OFW translations node.
While at it, ensure we are only taking valid OFW mapping entries
into account.
Revision Changes Path
1.18 +7 -4 src/sys/sparc64/include/tte.h
1.175 +10 -1 src/sys/sparc64/sparc64/pmap.c
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200809041943.m84JhXxf013190>