Date: Fri, 20 Nov 2009 17:17:18 -0800 From: "David Christensen" <davidch@broadcom.com> To: "Tom Judge" <tom@tomjudge.com> Cc: Gideon Naim <gideon.naim@broadcom.com>, "rwilliams@borderware.com" <rwilliams@borderware.com>, Miroslav Lachman <000.fbsd@quip.cz>, "net@freebsd.org" <net@freebsd.org> Subject: RE: bce(4) BCM5907 CTX write errors on 7.2 driver Message-ID: <5D267A3F22FD854F8F48B3D2B52381933A20E0F332@IRVEXCHCCR01.corp.ad.broadcom.com> In-Reply-To: <5D267A3F22FD854F8F48B3D2B52381933A20E0EFE1@IRVEXCHCCR01.corp.ad.broadcom.com> References: <4AE72910.8090708@tomjudge.com> <5D267A3F22FD854F8F48B3D2B52381933A04B49180@IRVEXCHCCR01.corp.ad.broadcom.com> <4AE76FF1.9010401@tomjudge.com> <5D267A3F22FD854F8F48B3D2B52381933A04B491AE@IRVEXCHCCR01.corp.ad.broadcom.com> <4AE8CC59.7020004@tomjudge.com> <4AE9D10F.4040703@tomjudge.com> <5D267A3F22FD854F8F48B3D2B52381933A054DE883@IRVEXCHCCR01.corp.ad.broadcom.com> <4AE9F576.4060101@tomjudge.com> <5D267A3F22FD854F8F48B3D2B52381933A19B35A55@IRVEXCHCCR01.corp.ad.broadcom.com> <4AEA0B11.2050209@tomjudge.com> <5D267A3F22FD854F8F48B3D2B52381933A19B35AB0@IRVEXCHCCR01.corp.ad.broadcom.com> <4AEA1183.7050306@tomjudge.com> <4AEB2571.7090006@tomjudge.com> <4AFAE428.5090907@quip.cz> <5D267A3F22FD854F8F48B3D2B52381933A20D4C55D@IRVEXCHCCR01.corp.ad.broadcom.com> <4AFAF542.8050004@tomjudge.com> <5D267A3F22FD854F8F48B3D2B52381933A20D4CA70@IRVEXCHCCR01.corp.ad.broadcom.com> <4AFC862B.6060805@tomjudge.com> <5D267A3F22FD854F8F48B3D2B52381933A20E0EFE1@IRVEXCHCCR01.corp.ad.broadcom.com>
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[-- Attachment #1 --]
> > For the record we also have not been able to reproduce the issue on
> > the R710 only the R610.
>
> I got hold of an R610 system and I now understand why the
> issue was difficult to replicate on R710. The R610 ships
> without Enterprise iDRAC while the R710 ship with the add-in
> Enterprise iDRAC module. When the module is present the
> system is managed through the additional RJ45 port but when
> the module is absent iDRAC traffic will flow through the
> on-board 5709 adpaters.
> The error will only occur when management firmware is loaded
> on the 5709 AND when NC-SI management functionality is enabled.
>
> You should be able to confirm this by adding or removing the
> Enterprise iDRAC module on your systems. Now that I have a
> failure again I have some ideas to test which might help.
> Stay tuned.
Does the attached patch make a difference for you?
FYI, I'll be out next week on vacation.
Dave
[-- Attachment #2 --]
--- if_bce.c.orig 2009-11-17 13:12:33.000000000 -0800
+++ if_bce.c 2009-11-20 16:26:55.000000000 -0800
@@ -371,6 +371,9 @@
static int bce_fw_sync (struct bce_softc *, u32);
static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32);
static void bce_load_cpu_fw (struct bce_softc *, struct cpu_reg *, struct fw_info *);
+static void bce_start_cpu (struct bce_softc *, struct cpu_reg *);
+static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *);
+static void bce_start_rxp_cpu (struct bce_softc *);
static void bce_init_rxp_cpu (struct bce_softc *);
static void bce_init_txp_cpu (struct bce_softc *);
static void bce_init_tpat_cpu (struct bce_softc *);
@@ -3667,15 +3670,10 @@
struct fw_info *fw)
{
u32 offset;
- u32 val;
DBENTER(BCE_VERBOSE_RESET);
- /* Halt the CPU. */
- val = REG_RD_IND(sc, cpu_reg->mode);
- val |= cpu_reg->mode_value_halt;
- REG_WR_IND(sc, cpu_reg->mode, val);
- REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
+ bce_halt_cpu(sc, cpu_reg);
/* Load the Text area. */
offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
@@ -3728,9 +3726,28 @@
}
}
- /* Clear the pre-fetch instruction. */
- REG_WR_IND(sc, cpu_reg->inst, 0);
- REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
+ /* Clear the pre-fetch instruction and set the FW start address. */
+ REG_WR_IND(sc, cpu_reg->inst, 0);
+ REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
+
+ DBEXIT(BCE_VERBOSE_RESET);
+}
+
+
+/****************************************************************************/
+/* Starts the RISC processor. */
+/* */
+/* Assumes the CPU starting address has already been set. */
+/* */
+/* Returns: */
+/* Nothing. */
+/****************************************************************************/
+static void
+bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
+{
+ u32 val;
+
+ DBENTER(BCE_VERBOSE_RESET);
/* Start the CPU. */
val = REG_RD_IND(sc, cpu_reg->mode);
@@ -3743,6 +3760,62 @@
/****************************************************************************/
+/* Halts the RISC processor. */
+/* */
+/* Returns: */
+/* Nothing. */
+/****************************************************************************/
+static void
+bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
+{
+ u32 val;
+
+ DBENTER(BCE_VERBOSE_RESET);
+
+ /* Halt the CPU. */
+ val = REG_RD_IND(sc, cpu_reg->mode);
+ val |= cpu_reg->mode_value_halt;
+ REG_WR_IND(sc, cpu_reg->mode, val);
+ REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
+
+ DBEXIT(BCE_VERBOSE_RESET);
+}
+
+
+/****************************************************************************/
+/* Initialize the RX CPU. */
+/* */
+/* Returns: */
+/* Nothing. */
+/****************************************************************************/
+static void
+bce_start_rxp_cpu(struct bce_softc *sc)
+{
+ struct cpu_reg cpu_reg;
+
+ DBENTER(BCE_VERBOSE_RESET);
+
+ cpu_reg.mode = BCE_RXP_CPU_MODE;
+ cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
+ cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
+ cpu_reg.state = BCE_RXP_CPU_STATE;
+ cpu_reg.state_value_clear = 0xffffff;
+ cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
+ cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
+ cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
+ cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
+ cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
+ cpu_reg.spad_base = BCE_RXP_SCRATCH;
+ cpu_reg.mips_view_base = 0x8000000;
+
+ DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
+ bce_start_cpu(sc, &cpu_reg);
+
+ DBEXIT(BCE_VERBOSE_RESET);
+}
+
+
+/****************************************************************************/
/* Initialize the RX CPU. */
/* */
/* Returns: */
@@ -3835,6 +3908,8 @@
DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
bce_load_cpu_fw(sc, &cpu_reg, &fw);
+ /* Delay RXP until initialization complete. */
+
DBEXIT(BCE_VERBOSE_RESET);
}
@@ -3931,6 +4006,7 @@
DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
bce_load_cpu_fw(sc, &cpu_reg, &fw);
+ bce_start_cpu(sc, &cpu_reg);
DBEXIT(BCE_VERBOSE_RESET);
}
@@ -4028,6 +4104,7 @@
DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
bce_load_cpu_fw(sc, &cpu_reg, &fw);
+ bce_start_cpu(sc, &cpu_reg);
DBEXIT(BCE_VERBOSE_RESET);
}
@@ -4125,6 +4202,7 @@
DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
bce_load_cpu_fw(sc, &cpu_reg, &fw);
+ bce_start_cpu(sc, &cpu_reg);
DBEXIT(BCE_VERBOSE_RESET);
}
@@ -4222,6 +4300,7 @@
DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
bce_load_cpu_fw(sc, &cpu_reg, &fw);
+ bce_start_cpu(sc, &cpu_reg);
DBEXIT(BCE_VERBOSE_RESET);
}
@@ -4667,6 +4746,12 @@
/* Initialize the on-boards CPUs */
bce_init_cpus(sc);
+ /* DRC - Management enable. */
+ if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
+ val = REG_RD(sc, 0x180c) | (1 << 31);
+ REG_WR(sc, 0x180c, val);
+ }
+
/* Prepare NVRAM for access. */
if (bce_init_nvram(sc)) {
rc = ENODEV;
@@ -4847,6 +4932,13 @@
/* Enable link state change interrupt generation. */
REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
+ /* DRC - Enable the RXP. */
+ bce_start_rxp_cpu(sc);
+ if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
+ val = REG_RD(sc, 0x180c) & ~(1 << 31);
+ REG_WR(sc, 0x180c, val);
+ }
+
/* Enable all remaining blocks in the MAC. */
if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
@@ -5856,7 +5948,7 @@
/* DRC _ Seeing problems when unloading with traffic. */
if(m0 == NULL) {
DBPRINT(sc, BCE_EXTREME_RECV, "%s(): Oops! Empty mbuf pointer "
- "in sc->rx_mbuf_ptr[0x%04X]!\n",
+ "found in sc->rx_mbuf_ptr[0x%04X]!\n",
__FUNCTION__, sw_rx_cons_idx);
goto bce_rx_int_next_rx;
}
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