Date: Thu, 29 Jul 2021 15:25:33 GMT From: Mitchell Horne <mhorne@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: d876c5a052fb - stable/13 - hwpmc_arm64: fill kern.hwpmc.cpuid Message-ID: <202107291525.16TFPXeC010014@gitrepo.freebsd.org>
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The branch stable/13 has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=d876c5a052fb589f213d20da2c146e5471047044 commit d876c5a052fb589f213d20da2c146e5471047044 Author: Mitchell Horne <mhorne@FreeBSD.org> AuthorDate: 2021-04-01 13:19:43 +0000 Commit: Mitchell Horne <mhorne@FreeBSD.org> CommitDate: 2021-07-29 15:01:11 +0000 hwpmc_arm64: fill kern.hwpmc.cpuid This will be used to detect supported pmu events. The expected format is the MIDR register with the revision and variant fields masked. See also: lib/libpmc/pmu-events/arch/arm64/mapfile.csv. MFC after: 2 weeks Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D30601 (cherry picked from commit 5867cccdc49df3e7eb3147d6516b488dd8384afe) --- sys/dev/hwpmc/hwpmc_arm64.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/sys/dev/hwpmc/hwpmc_arm64.c b/sys/dev/hwpmc/hwpmc_arm64.c index ba98eaefcc9a..be26605bad51 100644 --- a/sys/dev/hwpmc/hwpmc_arm64.c +++ b/sys/dev/hwpmc/hwpmc_arm64.c @@ -505,6 +505,7 @@ pmc_arm64_initialize() struct pmc_classdep *pcd; int idcode, impcode; int reg; + uint64_t midr; reg = arm64_pmcr_read(); arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT; @@ -513,6 +514,18 @@ pmc_arm64_initialize() PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs); + /* + * Write the CPU model to kern.hwpmc.cpuid. + * + * We zero the variant and revision fields. + * + * TODO: how to handle differences between cores due to big.LITTLE? + * For now, just use MIDR from CPU 0. + */ + midr = (uint64_t)(pcpu_find(0)->pc_midr); + midr &= ~(CPU_VAR_MASK | CPU_REV_MASK); + snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr); + /* * Allocate space for pointers to PMC HW descriptors and for * the MDEP structure used by MI code.
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