Date: Wed, 22 May 2002 17:28:34 +0800 From: "David Xu" <bsddiy@21cn.com> To: "Doug Rabson" <dfr@nlsystems.com>, <cvs-committers@freebsd.org>, <cvs-all@freebsd.org> Subject: Re: cvs commit: src/sys/i386/include cpufunc.h Message-ID: <000701c20173$0d5498f0$ef01a8c0@davidwnt> References: <200205212021.g4LKLsN48148@freefall.freebsd.org> <200205220947.11913.dfr@nlsystems.com>
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Cut from "IA-32 Intel=AE Architecture Software Developer's Manual Volume =
2: Instruction Set Reference",
here is the description:
PAUSE-Spin Loop Hint
Opcode Instruction Description
F3 90 PAUSE Gives hint to processor that improves performance of =
spin-wait
loops.
Description
Improves the performance of spin-wait loops. When executing a "spin-wait =
loop," a Pentium 4
or Intel Xeon processor suffers a severe performance penalty when =
exiting the loop because it
detects a possible memory order violation. The PAUSE instruction =
provides a hint to the
processor that the code sequence is a spin-wait loop. The processor uses =
this hint to avoid the
memory order violation in most situations, which greatly improves =
processor performance. For
this reason, it is recommended that a PAUSE instruction be placed in all =
spin-wait loops.
An additional function of the PAUSE instruction is to reduce the power =
consumed by a Pentium
4 processor while executing a spin loop. The Pentium 4 processor can =
execute a spin-wait loop
extremely quickly, causing the processor to consume a lot of power while =
it waits for the
resource it is spinning on to become available. Inserting a pause =
instruction in a spin-wait loop
greatly reduces the processor's power consumption.
This instruction was introduced in the Pentium 4 processors, but is =
backward compatible with
all IA-32 processors. In earlier IA-32 processors, the PAUSE instruction =
operates like a NOP
instruction. The Pentium 4 and Intel Xeon processors implement the PAUSE =
instruction as a
pre-defined delay. The delay is finite and can be zero for some =
processors. This instruction does
not change the architectural state of the processor (that is, it =
performs essentially a delaying noop
operation).
Operation
Execute_Next_Instruction(DELAY);
Protected Mode Exceptions
None.
Real-Address Mode Exceptions
None.
Virtual-8086 Mode Exceptions
None.
Numeric Exceptions
None.
--
David Xu
----- Original Message -----=20
From: "Doug Rabson" <dfr@nlsystems.com>
To: "John Baldwin" <jhb@FreeBSD.org>; <cvs-committers@FreeBSD.org>; =
<cvs-all@FreeBSD.org>
Sent: Wednesday, May 22, 2002 4:47 PM
Subject: Re: cvs commit: src/sys/i386/include cpufunc.h
On Tuesday 21 May 2002 9:21 pm, John Baldwin wrote:
> jhb 2002/05/21 13:21:54 PDT
>
> Modified files:
> sys/i386/include cpufunc.h
> Log:
> Add an inline function cpu_pause() for the IA32 'pause' instruction.
Is this the hyperthreading thing that you are supposed to call from the =
idle=20
loop?
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