Date: Tue, 1 Sep 2020 21:56:31 +0000 (UTC) From: Mateusz Guzik <mjg@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r365166 - head/sys/dev/qlxge Message-ID: <202009012156.081LuVYG047694@repo.freebsd.org>
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Author: mjg Date: Tue Sep 1 21:56:30 2020 New Revision: 365166 URL: https://svnweb.freebsd.org/changeset/base/365166 Log: qlxge: clean up empty lines in .c and .h files Modified: head/sys/dev/qlxge/qls_dbg.c head/sys/dev/qlxge/qls_dbg.h head/sys/dev/qlxge/qls_def.h head/sys/dev/qlxge/qls_dump.c head/sys/dev/qlxge/qls_dump.h head/sys/dev/qlxge/qls_hw.c head/sys/dev/qlxge/qls_hw.h head/sys/dev/qlxge/qls_ioctl.c head/sys/dev/qlxge/qls_ioctl.h head/sys/dev/qlxge/qls_isr.c head/sys/dev/qlxge/qls_os.c head/sys/dev/qlxge/qls_os.h Modified: head/sys/dev/qlxge/qls_dbg.c ============================================================================== --- head/sys/dev/qlxge/qls_dbg.c Tue Sep 1 21:56:10 2020 (r365165) +++ head/sys/dev/qlxge/qls_dbg.c Tue Sep 1 21:56:30 2020 (r365166) @@ -41,7 +41,6 @@ __FBSDID("$FreeBSD$"); #include "qls_glbl.h" #include "qls_dbg.h" - uint32_t qls_dbg_level = 0 ; /* * Name: qls_dump_buf32 @@ -162,7 +161,7 @@ qls_dump_buf8(qla_host_t *ha, const char *msg, void *d buf = dbuf; device_printf(dev, "%s: %s 0x%x dump start\n", __func__, msg, len); - + while (len >= 16) { device_printf(dev,"0x%08x:" " %02x %02x %02x %02x %02x %02x %02x %02x" @@ -265,7 +264,7 @@ qls_dump_buf8(qla_host_t *ha, const char *msg, void *d default: break; } - + device_printf(dev, "%s: %s dump end\n", __func__, msg); return; @@ -306,4 +305,3 @@ qls_dump_cq(qla_host_t *ha) return; } - Modified: head/sys/dev/qlxge/qls_dbg.h ============================================================================== --- head/sys/dev/qlxge/qls_dbg.h Tue Sep 1 21:56:10 2020 (r365165) +++ head/sys/dev/qlxge/qls_dbg.h Tue Sep 1 21:56:30 2020 (r365166) @@ -48,7 +48,6 @@ extern void qls_dump_buf32(qla_host_t *ha, const char extern void qls_dump_cq(qla_host_t *ha); - #ifdef QL_DBG #define QL_DPRINT1(x) if (qls_dbg_level & 0x0001) device_printf x @@ -91,6 +90,5 @@ extern void qls_dump_cq(qla_host_t *ha); #define QL_DUMP_CQ(ha) #endif - #endif /* #ifndef _QL_DBG_H_ */ Modified: head/sys/dev/qlxge/qls_def.h ============================================================================== --- head/sys/dev/qlxge/qls_def.h Tue Sep 1 21:56:10 2020 (r365165) +++ head/sys/dev/qlxge/qls_def.h Tue Sep 1 21:56:30 2020 (r365166) @@ -96,7 +96,6 @@ struct qla_tx_buf { typedef struct qla_tx_buf qla_tx_buf_t; struct qla_tx_ring { - volatile struct { uint32_t wq_dma:1, privb_dma:1; @@ -119,7 +118,7 @@ struct qla_tx_ring { uint32_t *txr_cons_vaddr; bus_addr_t txr_cons_paddr; - + volatile uint32_t txr_free; /* # of free entries in tx ring */ volatile uint32_t txr_next; /* # next available tx ring entry */ volatile uint32_t txr_done; @@ -147,7 +146,6 @@ typedef struct qla_tx_ring qla_tx_ring_t; #define QLA_LGBQ_AND_TABLE_SIZE \ ((QLA_LBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1)) - /* Please note that Small Buffer size is determined by max mtu size */ #define QLA_NUM_SMB_ENTRIES NUM_RX_DESCRIPTORS @@ -222,7 +220,6 @@ struct qla_rx_ring { }; typedef struct qla_rx_ring qla_rx_ring_t; - #define QLA_WATCHDOG_CALLOUT_TICKS 1 /* @@ -326,7 +323,7 @@ struct qla_host { uint8_t mac_addr[ETHER_ADDR_LEN]; uint32_t nmcast; qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS]; - + /* Link Related */ uint8_t link_up; uint32_t link_status; @@ -358,7 +355,7 @@ struct qla_host { /* mpi dump related */ qla_dma_t mpi_dma; qla_dma_t rss_dma; - + }; typedef struct qla_host qla_host_t; Modified: head/sys/dev/qlxge/qls_dump.c ============================================================================== --- head/sys/dev/qlxge/qls_dump.c Tue Sep 1 21:56:10 2020 (r365165) +++ head/sys/dev/qlxge/qls_dump.c Tue Sep 1 21:56:30 2020 (r365166) @@ -33,7 +33,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); - #include "qls_os.h" #include "qls_hw.h" #include "qls_def.h" @@ -380,7 +379,6 @@ qls_wait_reg_rdy(qla_host_t *ha , uint32_t reg, uint32 int count = 10; while (count) { - data = READ_REG32(ha, reg); if (data & err_bit) @@ -439,7 +437,6 @@ exit_qls_wr_mpi_reg: return (ret); } - #define Q81_TEST_LOGIC_FUNC_PORT_CONFIG 0x1002 #define Q81_INVALID_NUM 0xFFFFFFFF @@ -528,7 +525,6 @@ qls_wait_ofunc_reg_rdy(qla_host_t *ha , uint32_t reg, int count = 10; while (count) { - data = qls_rd_ofunc_reg(ha, reg); if (data & err_bit) @@ -685,7 +681,6 @@ qls_rd_serdes_regs(qla_host_t *ha, qls_mpi_coredump_t temp = 0; if ((temp & Q81_XFI1_POWERED_UP) == Q81_XFI1_POWERED_UP) { - if (ha->pci_func & 1) xfi_ind_valid = 1; /* NIC 2, so the indirect (NIC1) xfi is up*/ @@ -694,7 +689,6 @@ qls_rd_serdes_regs(qla_host_t *ha, qls_mpi_coredump_t } if((temp & Q81_XFI2_POWERED_UP) == Q81_XFI2_POWERED_UP) { - if(ha->pci_func & 1) xfi_d_valid = 1; /* NIC 2, so the indirect (NIC1) xfi is up */ @@ -855,7 +849,6 @@ qls_get_intr_states(qla_host_t *ha, uint32_t *buf) int i; for (i = 0; i < MAX_RX_RINGS; i++, buf++) { - WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i)); *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE); @@ -892,7 +885,6 @@ qls_rd_xgmac_regs(qla_host_t *ha, uint32_t *buf, uint3 int i; for (i = 0; i < Q81_XGMAC_REGISTER_END; i += 4, buf ++) { - switch (i) { case Q81_PAUSE_SRC_LO : case Q81_PAUSE_SRC_HI : @@ -1158,7 +1150,6 @@ qls_rd_xgmac_regs(qla_host_t *ha, uint32_t *buf, uint3 default: break; - } } return 0; @@ -1170,7 +1161,6 @@ qls_get_mpi_regs(qla_host_t *ha, uint32_t *buf, uint32 int i, ret = 0; for (i = 0; i < count; i++, buf++) { - ret = qls_rd_mpi_reg(ha, (offset + i), buf); if (ret) @@ -1191,7 +1181,6 @@ qls_get_mpi_shadow_regs(qla_host_t *ha, uint32_t *buf) #define Q81_SHADOW_OFFSET 0xb0000000 for (i = 0; i < Q81_MPI_CORE_SH_REGS_CNT; i++, buf++) { - ret = qls_wr_mpi_reg(ha, (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_124), (Q81_SHADOW_OFFSET | i << 20)); @@ -1225,11 +1214,8 @@ qls_get_probe(qla_host_t *ha, uint32_t clock, uint8_t uint32_t module, mux_sel, probe, lo_val, hi_val; for (module = 0; module < Q81_MAX_MODULES; module ++) { - if (valid[module]) { - for (mux_sel = 0; mux_sel < Q81_MAX_MUX; mux_sel++) { - probe = clock | Q81_ADDRESS_REGISTER_ENABLE | mux_sel | (module << 9); WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ @@ -1300,7 +1286,6 @@ qls_get_probe_dump(qla_host_t *ha, uint32_t *buf) 0 // 0x1F }; - uint8_t pci_clock_valid_modules[0x20] = { 1, // 0x00 0, // 0x01 @@ -1336,7 +1321,6 @@ qls_get_probe_dump(qla_host_t *ha, uint32_t *buf) 0 // 0x1F }; - uint8_t xgm_clock_valid_modules[0x20] = { 1, // 0x00 0, // 0x01 @@ -1435,7 +1419,6 @@ qls_get_ridx_registers(qla_host_t *ha, uint32_t *buf) idx_max = 16; for (idx = 0; idx < idx_max; idx ++) { - val = 0x04000000 | (type << 16) | (idx << 8); WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, val); @@ -1476,7 +1459,6 @@ qls_get_mac_proto_regs(qla_host_t *ha, uint32_t* buf) for (type = 0; type < Q81_NUM_TYPES; type ++) { switch (type) { - case 0: // CAM initial_val = Q81_RS_AND_ADR; max_index = 512; @@ -1540,9 +1522,7 @@ qls_get_mac_proto_regs(qla_host_t *ha, uint32_t* buf) } for (index = 0; index < max_index; index ++) { - for (offset = 0; offset < max_offset; offset ++) { - val = initial_val | (type << 16) | (index << 4) | (offset); @@ -1663,7 +1643,6 @@ qls_mpi_core_dump(qla_host_t *ha) qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 1); } - qls_mpid_seg_hdr(&mpi_dump->xaui1_an_hdr, Q81_XAUI1_AN_SEG_NUM, (sizeof(qls_mpid_seg_hdr_t) + @@ -1928,7 +1907,6 @@ qls_mpi_core_dump(qla_host_t *ha) "Sem Registers"); for(i = 0; i < Q81_MAX_SEMAPHORE_FUNCTIONS ; i ++) { - reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (i << Q81_FUNCTION_SHIFT) | (Q81_CTL_SEMAPHORE >> 2); @@ -1991,4 +1969,3 @@ qls_mpi_core_dump(qla_host_t *ha) return 0; } - Modified: head/sys/dev/qlxge/qls_dump.h ============================================================================== --- head/sys/dev/qlxge/qls_dump.h Tue Sep 1 21:56:10 2020 (r365165) +++ head/sys/dev/qlxge/qls_dump.h Tue Sep 1 21:56:30 2020 (r365166) @@ -276,4 +276,3 @@ typedef struct qls_mpi_coredump qls_mpi_coredump_t; #define Q81_BAD_DATA 0xDEADBEEF #endif /* #ifndef _QLS_DUMP_H_ */ - Modified: head/sys/dev/qlxge/qls_hw.c ============================================================================== --- head/sys/dev/qlxge/qls_hw.c Tue Sep 1 21:56:10 2020 (r365165) +++ head/sys/dev/qlxge/qls_hw.c Tue Sep 1 21:56:30 2020 (r365166) @@ -35,8 +35,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); - - #include "qls_os.h" #include "qls_hw.h" #include "qls_def.h" @@ -76,7 +74,6 @@ static int qls_alloc_rss_dma(qla_host_t *ha); static int qls_flash_validate(qla_host_t *ha, const char *signature); - static int qls_wait_for_proc_addr_ready(qla_host_t *ha); static int qls_proc_addr_rd_reg(qla_host_t *ha, uint32_t addr_module, uint32_t reg, uint32_t *data); @@ -112,7 +109,6 @@ qls_syctl_mpi_dump(SYSCTL_HANDLER_ARGS) if (err || !req->newptr) return (err); - if (ret == 1) { ha = (qla_host_t *)arg1; qls_mpi_core_dump(ha); @@ -131,7 +127,6 @@ qls_syctl_link_status(SYSCTL_HANDLER_ARGS) if (err || !req->newptr) return (err); - if (ret == 1) { ha = (qla_host_t *)arg1; qls_mbx_get_link_status(ha); @@ -217,7 +212,6 @@ qls_alloc_dma(qla_host_t *ha) return (0); } - static int qls_wait_for_mac_proto_idx_ready(qla_host_t *ha, uint32_t op) { @@ -262,7 +256,7 @@ qls_config_unicast_mac_addr(qla_host_t *ha, uint32_t a ret = qls_wait_for_mac_proto_idx_ready(ha, Q81_CTL_MAC_PROTO_AI_MW); if (ret) goto qls_config_unicast_mac_addr_exit; - + index = 128 * (ha->pci_func & 0x1); /* index */ value = (index << Q81_CTL_MAC_PROTO_AI_IDX_SHIFT) | @@ -328,7 +322,7 @@ qls_config_mcast_mac_addr(qla_host_t *ha, uint8_t *mac ret = qls_wait_for_mac_proto_idx_ready(ha, Q81_CTL_MAC_PROTO_AI_MW); if (ret) goto qls_config_mcast_mac_addr_exit; - + value = Q81_CTL_MAC_PROTO_AI_E | (index << Q81_CTL_MAC_PROTO_AI_IDX_SHIFT) | Q81_CTL_MAC_PROTO_AI_TYPE_MCAST ; @@ -388,7 +382,6 @@ qls_load_route_idx_reg(qla_host_t *ha, uint32_t index, goto qls_load_route_idx_reg_exit; } - WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, index); WRITE_REG32(ha, Q81_CTL_ROUTING_DATA, data); @@ -481,7 +474,6 @@ qls_reset_allmulti(qla_host_t *ha) return; } - static int qls_init_fw_routing_table(qla_host_t *ha) { @@ -596,7 +588,6 @@ qls_tx_tso_chksum(qla_host_t *ha, struct mbuf *mp, q81 } tx_mac->vlan_off |= Q81_TX_TSO_VLAN_OFF_IC ; - if (ip->ip_p == IPPROTO_TCP) { tx_mac->flags |= Q81_TX_TSO_FLAGS_TC; } else if (ip->ip_p == IPPROTO_UDP) { @@ -702,10 +693,9 @@ qls_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, i tx_mac = (q81_tx_mac_t *)&ha->tx_ring[txr_idx].wq_vaddr[txr_next]; bzero(tx_mac, sizeof(q81_tx_mac_t)); - + if ((mp->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO)) != 0) { - ret = qls_tx_tso_chksum(ha, mp, (q81_tx_tso_t *)tx_mac); if (ret) return (EINVAL); @@ -720,7 +710,6 @@ qls_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, i } if (mp->m_flags & M_VLANTAG) { - tx_mac->vlan_tci = mp->m_pkthdr.ether_vtag; tx_mac->vlan_off |= Q81_TX_MAC_VLAN_OFF_V; @@ -732,7 +721,6 @@ qls_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, i tx_mac->tid_lo = txr_next; if (nsegs <= MAX_TX_MAC_DESC) { - QL_DPRINT2((dev, "%s: 1 [%d, %d]\n", __func__, total_length, tx_mac->tid_lo)); @@ -832,7 +820,6 @@ qls_init_hw_if(qla_host_t *ha) int ret = 0; int i; - QL_DPRINT2((ha->pci_dev, "%s:enter\n", __func__)); dev = ha->pci_dev; @@ -871,7 +858,7 @@ qls_init_hw_if(qla_host_t *ha) /* Interrupt Mask Register */ value = Q81_CTL_INTRM_PI; value = (value << Q81_CTL_INTRM_MASK_SHIFT) | value; - + WRITE_REG32(ha, Q81_CTL_INTR_MASK, value); /* Initialiatize Completion Queue */ @@ -945,7 +932,6 @@ qls_init_hw_if(qla_host_t *ha) ha->tx_ring[0].wq_db_offset)); for (i = 0; i < ha->num_rx_rings; i++) { - Q81_WR_CQ_CONS_IDX(i, 0); Q81_WR_LBQ_PROD_IDX(i, ha->rx_ring[i].lbq_in); Q81_WR_SBQ_PROD_IDX(i, ha->rx_ring[i].sbq_in); @@ -972,7 +958,6 @@ qls_wait_for_config_reg_bits(qla_host_t *ha, uint32_t uint32_t count = 3; while (count--) { - data32 = READ_REG32(ha, Q81_CTL_CONFIG); if ((data32 & bits) == value) @@ -1076,7 +1061,7 @@ qls_init_comp_queue(qla_host_t *ha, int cid) Q81_CQ_ICB_FLAGS_LL | Q81_CQ_ICB_FLAGS_LS | Q81_CQ_ICB_FLAGS_LV; - + cq_icb->length_v = NUM_CQ_ENTRIES; cq_icb->cq_baddr_lo = (rxr->cq_base_paddr & 0xFFFFFFFF); @@ -1221,7 +1206,6 @@ qls_hw_add_all_mcast(qla_host_t *ha) (ha->mcast[i].addr[3] != 0) || (ha->mcast[i].addr[4] != 0) || (ha->mcast[i].addr[5] != 0)) { - if (qls_config_mcast_mac_addr(ha, ha->mcast[i].addr, 1, i)) { device_printf(ha->pci_dev, "%s: failed\n", @@ -1241,20 +1225,17 @@ qls_hw_add_mcast(qla_host_t *ha, uint8_t *mta) int i; for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { - if (QL_MAC_CMP(ha->mcast[i].addr, mta) == 0) return 0; /* its been already added */ } for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { - if ((ha->mcast[i].addr[0] == 0) && (ha->mcast[i].addr[1] == 0) && (ha->mcast[i].addr[2] == 0) && (ha->mcast[i].addr[3] == 0) && (ha->mcast[i].addr[4] == 0) && (ha->mcast[i].addr[5] == 0)) { - if (qls_config_mcast_mac_addr(ha, mta, 1, i)) return (-1); @@ -1274,7 +1255,6 @@ qls_hw_del_mcast(qla_host_t *ha, uint8_t *mta) for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { if (QL_MAC_CMP(ha->mcast[i].addr, mta) == 0) { - if (qls_config_mcast_mac_addr(ha, mta, 0, i)) return (-1); @@ -1338,8 +1318,6 @@ qls_update_link_state(qla_host_t *ha) ha->link_up = ((link_state & Q81_CTL_STATUS_PL1)? 1 : 0); if (prev_link_state != ha->link_up) { - - if (ha->link_up) { if_link_state_change(ha->ifp, LINK_STATE_UP); } else { @@ -1371,11 +1349,9 @@ qls_free_tx_dma(qla_host_t *ha) qla_tx_buf_t *txb; for (i = 0; i < ha->num_tx_rings; i++) { - qls_free_tx_ring_dma(ha, i); for (j = 0; j < NUM_TX_DESCRIPTORS; j++) { - txb = &ha->tx_ring[i].tx_buf[j]; if (txb->map) { @@ -1444,7 +1420,6 @@ qls_alloc_tx_ring_dma(qla_host_t *ha, int ridx) txb = ha->tx_ring[ridx].tx_buf; for (i = 0; i < NUM_TX_DESCRIPTORS; i++) { - txb[i].oal_vaddr = v_addr; txb[i].oal_paddr = p_addr; @@ -1481,7 +1456,6 @@ qls_alloc_tx_dma(qla_host_t *ha) } for (i = 0; i < ha->num_tx_rings; i++) { - ret = qls_alloc_tx_ring_dma(ha, i); if (ret) { @@ -1490,7 +1464,6 @@ qls_alloc_tx_dma(qla_host_t *ha) } for (j = 0; j < NUM_TX_DESCRIPTORS; j++) { - txb = &ha->tx_ring[i].tx_buf[j]; ret = bus_dmamap_create(ha->tx_tag, @@ -1691,7 +1664,7 @@ qls_alloc_rx_ring_dma(qla_host_t *ha, int ridx) /* large buffer queue */ ha->rx_ring[ridx].lbq_vaddr = v_addr + PAGE_SIZE; ha->rx_ring[ridx].lbq_paddr = p_addr + PAGE_SIZE; - + v_addr = ha->rx_ring[ridx].sbq_dma.dma_b; p_addr = ha->rx_ring[ridx].sbq_dma.dma_addr; @@ -1760,7 +1733,6 @@ qls_alloc_rx_dma(qla_host_t *ha) NULL, /* lockfunc */ NULL, /* lockfuncarg */ &ha->rx_tag)) { - device_printf(ha->pci_dev, "%s: rx_tag alloc failed\n", __func__); @@ -1786,7 +1758,6 @@ qls_wait_for_flash_ready(qla_host_t *ha) uint32_t count = 3; while (count--) { - data32 = READ_REG32(ha, Q81_CTL_FLASH_ADDR); if (data32 & Q81_CTL_FLASH_ADDR_ERR) @@ -1878,7 +1849,6 @@ qls_rd_nic_params(qla_host_t *ha) qflash = (uint32_t *)&ha->flash; for (i = 0; i < (sizeof(q81_flash_t) >> 2) ; i++) { - ret = qls_rd_flash32(ha, faddr, qflash); if (ret) @@ -1916,7 +1886,7 @@ qls_sem_lock(qla_host_t *ha, uint32_t mask, uint32_t v while (count--) { WRITE_REG32(ha, Q81_CTL_SEMAPHORE, (mask|value)); - + data = READ_REG32(ha, Q81_CTL_SEMAPHORE); if (data & value) { @@ -1942,7 +1912,6 @@ qls_wait_for_proc_addr_ready(qla_host_t *ha) uint32_t count = 3; while (count--) { - data32 = READ_REG32(ha, Q81_CTL_PROC_ADDR); if (data32 & Q81_CTL_PROC_ADDR_ERR) @@ -1981,7 +1950,7 @@ qls_proc_addr_rd_reg(qla_host_t *ha, uint32_t addr_mod if (ret) goto qls_proc_addr_rd_reg_exit; - + *data = READ_REG32(ha, Q81_CTL_PROC_DATA); qls_proc_addr_rd_reg_exit: @@ -2018,7 +1987,7 @@ qls_hw_nic_reset(qla_host_t *ha) int count; uint32_t data; device_t dev = ha->pci_dev; - + ha->hw_init = 0; data = (Q81_CTL_RESET_FUNC << Q81_CTL_RESET_MASK_SHIFT) | @@ -2039,7 +2008,7 @@ qls_hw_nic_reset(qla_host_t *ha) } return (0); } - + static int qls_hw_reset(qla_host_t *ha) { @@ -2096,7 +2065,7 @@ qls_hw_reset(qla_host_t *ha) ret = qls_hw_nic_reset(ha); if (ret) goto qls_hw_reset_exit; - + ret = qls_mbx_set_mgmt_ctrl(ha, Q81_MBX_SET_MGMT_CTL_RESUME); qls_hw_reset_exit: @@ -2159,7 +2128,6 @@ qls_mbx_wr_reg(qla_host_t *ha, uint32_t reg, uint32_t return (ret); } - static int qls_mbx_cmd(qla_host_t *ha, uint32_t *in_mbx, uint32_t i_count, uint32_t *out_mbx, uint32_t o_count) @@ -2190,7 +2158,6 @@ qls_mbx_cmd(qla_host_t *ha, uint32_t *in_mbx, uint32_t mbx_cmd = *in_mbx; for (i = 0; i < i_count; i++) { - ret = qls_mbx_wr_reg(ha, i, *in_mbx); if (ret) { @@ -2211,7 +2178,6 @@ qls_mbx_cmd(qla_host_t *ha, uint32_t *in_mbx, uint32_t ha->mbx_done = 0; while (count--) { - if (ha->flags.intr_enable == 0) { data32 = READ_REG32(ha, Q81_CTL_STATUS); @@ -2224,7 +2190,6 @@ qls_mbx_cmd(qla_host_t *ha, uint32_t *in_mbx, uint32_t if (ret == 0 ) { if ((data32 & 0xF000) == 0x4000) { - out_mbx[0] = data32; for (i = 1; i < o_count; i++) { @@ -2422,7 +2387,7 @@ qls_mpi_reset(qla_host_t *ha) int count; uint32_t data; device_t dev = ha->pci_dev; - + WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\ Q81_CTL_HCS_CMD_SET_RISC_RESET); @@ -2442,4 +2407,3 @@ qls_mpi_reset(qla_host_t *ha) } return (0); } - Modified: head/sys/dev/qlxge/qls_hw.h ============================================================================== --- head/sys/dev/qlxge/qls_hw.h Tue Sep 1 21:56:10 2020 (r365165) +++ head/sys/dev/qlxge/qls_hw.h Tue Sep 1 21:56:30 2020 (r365166) @@ -86,7 +86,6 @@ #define BIT_30 (0x1 << 30) #define BIT_31 (0x1 << 31) - /* * Firmware Interface */ @@ -169,7 +168,6 @@ #define Q81_CTL_XG_PROBE_MUX_ADDR 0xF8 /* R/W - Y - */ #define Q81_CTL_XG_PROBE_MUX_DATA 0xFC /* R/W - Y - */ - /* * Process Address Register (0x00) */ @@ -181,7 +179,6 @@ #define Q81_CTL_PROC_ADDR_REG_BLOCK (0x02 << 16) #define Q81_CTL_PROC_ADDR_RISC_INT_REG (0x03 << 16) - /* * System Register (0x08) */ @@ -228,7 +225,6 @@ #define Q81_CTL_FUNC_SPECIFIC_DBRST_768 0x02 #define Q81_CTL_FUNC_SPECIFIC_DBRST_1024 0x03 - /* * Host Command/Status Register (0x14) */ @@ -250,7 +246,6 @@ #define Q81_CTL_HCS_RISC_RESET BIT_8 #define Q81_CTL_HCS_ERR_STATUS_MASK 0x3F - /* * Configuration Register (0x28) */ @@ -265,7 +260,6 @@ #define Q81_CTL_CONFIG_DRQ BIT_1 #define Q81_CTL_CONFIG_LRQ BIT_0 - /* * Status Register (0x30) */ @@ -363,7 +357,6 @@ #define Q81_CTL_SEM_SET_XGMAC1 0x0004 #define Q81_CTL_SEM_SET_XGMAC0 0x0001 - /* * Flash Address Register (0x88) */ @@ -439,7 +432,6 @@ #define Q81_CTL_NIC_RCVC_VLAN_REJECT (0x3 << 1) #define Q81_CTL_NIC_RCVC_PPE BIT_0 - /* * Routing Index Register (0xE4) */ @@ -505,7 +497,6 @@ #define Q81_CTL_RD_RSS_IPV4 BIT_30 #define Q81_CTL_RD_RSS_MATCH BIT_31 - /********************************************************************* * Host Data Structures * *********************************************************************/ @@ -515,7 +506,6 @@ */ typedef struct _q81_wq_icb { - uint16_t length_v; #define Q81_WQ_ICB_VALID BIT_4 @@ -540,7 +530,6 @@ typedef struct _q81_wq_icb { uint32_t ci_addr_hi; } __packed q81_wq_icb_t; - /* * Completion Queue Initialization Control Block */ @@ -606,8 +595,6 @@ typedef struct _q81_rss_icb { uint32_t ipv4_rss_hash_key[4]; } __packed q81_rss_icb_t; - - /* * Transmit Buffer Descriptor */ @@ -622,7 +609,6 @@ typedef struct _q81_txb_desc { } __packed q81_txb_desc_t; - /* * Receive Buffer Descriptor */ @@ -651,7 +637,6 @@ typedef struct _q81_rxb_desc { #define Q81_IOCB_MPI 0x21 #define Q81_IOCB_SYS 0x3F - /* * IOCB Definitions */ @@ -663,7 +648,6 @@ typedef struct _q81_rxb_desc { #define MAX_TX_MAC_DESC 8 typedef struct _q81_tx_mac { - uint8_t opcode; uint16_t flags; @@ -692,8 +676,7 @@ typedef struct _q81_tx_mac { q81_txb_desc_t txd[MAX_TX_MAC_DESC]; } __packed q81_tx_mac_t; - - + /* * MAC Tx Frame with TSO IOCB * Total Size of each IOCB Entry = 4 * 32 = 128 bytes @@ -734,7 +717,7 @@ typedef struct _q81_tx_tso { q81_txb_desc_t txd[MAX_TX_MAC_DESC]; } __packed q81_tx_tso_t; - + typedef struct _q81_tx_cmd { uint8_t bytes[128]; } __packed q81_tx_cmd_t; @@ -766,7 +749,6 @@ typedef struct _q81_tx_mac_comp { uint32_t rsrvd1[13]; } __packed q81_tx_mac_comp_t; - /* * MAC TX Frame with LSO Completion * Total Size of each IOCB Entry = 4 * 16 = 64 bytes @@ -793,7 +775,6 @@ typedef struct _q81_tx_tso_comp { uint32_t rsrvd1[13]; } __packed q81_tx_tso_comp_t; - /* * SYS - Chip Event Notification Completion * Total Size of each IOCB Entry = 4 * 16 = 64 bytes @@ -823,8 +804,6 @@ typedef struct _q81_sys_comp { uint32_t rsrvd1[15]; } __packed q81_sys_comp_t; - - /* * Mac Rx Packet Completion * Total Size of each IOCB Entry = 4 * 16 = 64 bytes @@ -904,7 +883,6 @@ typedef struct _q81_bq_addr_e { uint32_t addr_hi; } __packed q81_bq_addr_e_t; - /* * Macros for reading and writing registers */ @@ -946,7 +924,6 @@ typedef struct _q81_bq_addr_e { #define Q81_RD_WQ_IDX(wq_idx) bus_read_4((ha->pci_reg1),\ (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG)) - #define Q81_SET_WQ_VALID(wq_idx) bus_write_4((ha->pci_reg1),\ (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\ Q81_COMPQ_VALID_V) @@ -981,7 +958,6 @@ typedef struct _q81_bq_addr_e { #define Q81_RD_SBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG)) - /* * Flash Related */ @@ -991,7 +967,6 @@ typedef struct _q81_bq_addr_e { #define Q81_FLASH_ID "8000" typedef struct _q81_flash { - uint8_t id[4]; /* equal to "8000" */ uint16_t version; @@ -1024,7 +999,6 @@ typedef struct _q81_flash { uint8_t rsrvd2[4]; } __packed q81_flash_t; - /* * MPI Related Modified: head/sys/dev/qlxge/qls_ioctl.c ============================================================================== --- head/sys/dev/qlxge/qls_ioctl.c Tue Sep 1 21:56:10 2020 (r365165) +++ head/sys/dev/qlxge/qls_ioctl.c Tue Sep 1 21:56:30 2020 (r365166) @@ -33,7 +33,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); - #include "qls_os.h" #include "qls_hw.h" #include "qls_def.h" @@ -95,7 +94,6 @@ qls_eioctl(struct cdev *dev, u_long cmd, caddr_t data, pci_dev= ha->pci_dev; switch(cmd) { - case QLA_MPI_DUMP: mpi_dump = (qls_mpi_dump_t *)data; @@ -119,7 +117,6 @@ qls_eioctl(struct cdev *dev, u_long cmd, caddr_t data, __func__, rval); } } - } break; @@ -129,4 +126,3 @@ qls_eioctl(struct cdev *dev, u_long cmd, caddr_t data, return rval; } - Modified: head/sys/dev/qlxge/qls_ioctl.h ============================================================================== --- head/sys/dev/qlxge/qls_ioctl.h Tue Sep 1 21:56:10 2020 (r365165) +++ head/sys/dev/qlxge/qls_ioctl.h Tue Sep 1 21:56:30 2020 (r365166) @@ -49,5 +49,4 @@ typedef struct qls_mpi_dump qls_mpi_dump_t; */ #define QLA_MPI_DUMP _IOWR('q', 1, qls_mpi_dump_t) - #endif /* #ifndef _QLS_IOCTL_H_ */ Modified: head/sys/dev/qlxge/qls_isr.c ============================================================================== --- head/sys/dev/qlxge/qls_isr.c Tue Sep 1 21:56:10 2020 (r365165) +++ head/sys/dev/qlxge/qls_isr.c Tue Sep 1 21:56:30 2020 (r365166) @@ -36,8 +36,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); - - #include "qls_os.h" #include "qls_hw.h" #include "qls_def.h" @@ -46,7 +44,6 @@ __FBSDID("$FreeBSD$"); #include "qls_glbl.h" #include "qls_dbg.h" - static void qls_tx_comp(qla_host_t *ha, uint32_t txr_idx, q81_tx_mac_comp_t *tx_comp) { @@ -90,7 +87,6 @@ qls_replenish_rx(qla_host_t *ha, uint32_t r_idx) sbq_e = rxr->sbq_vaddr; while (count--) { - rxb = &rxr->rx_buf[rxr->sbq_next]; if (rxb->m_head == NULL) { @@ -117,7 +113,6 @@ qls_replenish_rx(qla_host_t *ha, uint32_t r_idx) } if (rxr->sbq_free == 16) { - rxr->sbq_in += 16; rxr->sbq_in = rxr->sbq_in & (NUM_RX_DESCRIPTORS - 1); rxr->sbq_free = 0; @@ -149,7 +144,6 @@ qls_rx_comp(qla_host_t *ha, uint32_t rxr_idx, uint32_t return -1; } if (rxb->paddr != cq_e->b_paddr) { - device_printf(dev, "%s: (rxb->paddr != cq_e->b_paddr)[%p, %p] \n", __func__, (void *)rxb->paddr, (void *)cq_e->b_paddr); @@ -164,7 +158,6 @@ qls_rx_comp(qla_host_t *ha, uint32_t rxr_idx, uint32_t rxr->rx_int++; if ((cq_e->flags1 & Q81_RX_FLAGS1_ERR_MASK) == 0) { - mp = rxb->m_head; rxb->m_head = NULL; @@ -245,11 +238,9 @@ qls_cq_isr(qla_host_t *ha, uint32_t cq_idx) i = ha->rx_ring[cq_idx].cq_next; while (i != cq_comp_idx) { - cq_e = &cq_b[i]; switch (cq_e->opcode) { - case Q81_IOCB_TX_MAC: case Q81_IOCB_TX_TSO: qls_tx_comp(ha, cq_idx, (q81_tx_mac_comp_t *)cq_e); @@ -258,7 +249,7 @@ qls_cq_isr(qla_host_t *ha, uint32_t cq_idx) case Q81_IOCB_RX: ret = qls_rx_comp(ha, cq_idx, i, (q81_rx_t *)cq_e); - + break; case Q81_IOCB_MPI: @@ -311,7 +302,6 @@ qls_mbx_isr(qla_host_t *ha) device_t dev = ha->pci_dev; if (qls_mbx_rd_reg(ha, 0, &data) == 0) { - if ((data & 0xF000) == 0x4000) { ha->mbox[0] = data; for (i = 1; i < Q81_NUM_MBX_REGISTERS; i++) { @@ -321,9 +311,8 @@ qls_mbx_isr(qla_host_t *ha) } ha->mbx_done = 1; } else if ((data & 0xF000) == 0x8000) { - /* we have an AEN */ - + ha->aen[0] = data; for (i = 1; i < Q81_NUM_AEN_REGISTERS; i++) { if (qls_mbx_rd_reg(ha, i, &data)) @@ -339,7 +328,6 @@ qls_mbx_isr(qla_host_t *ha) ha->aen[6], ha->aen[7], ha->aen[8]); switch ((ha->aen[0] & 0xFFFF)) { - case 0x8011: ha->link_up = 1; break; @@ -355,7 +343,6 @@ qls_mbx_isr(qla_host_t *ha) case 0x8131: ha->link_hw_info = 0; break; - } } } @@ -397,4 +384,3 @@ qls_isr(void *arg) return; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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