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Date:      Wed, 20 Oct 1999 14:46:00 -0400 (EDT)
From:      kbyanc@posi.net
To:        FreeBSD-gnats-submit@freebsd.org
Subject:   i386/14438: additional CPUID bit definitions for identcpu.c
Message-ID:  <199910201846.OAA36515@kronos.alcnet.com>

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>Number:         14438
>Category:       i386
>Synopsis:       additional CPUID bit definitions for identcpu.c
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    freebsd-bugs
>State:          open
>Quarter:        
>Keywords:       
>Date-Required:
>Class:          change-request
>Submitter-Id:   current-users
>Arrival-Date:   Wed Oct 20 11:50:01 PDT 1999
>Closed-Date:
>Last-Modified:
>Originator:     Kelly Yancey
>Release:        FreeBSD 3.2-STABLE i386
>Organization:
>Environment:

  Attached patch applies to (from -current):
$FreeBSD: src/sys/i386/i386/identcpu.c,v 1.77 1999/10/14 13:59:52 kato Exp $

  Also applies to -stable's identcpu.c after applying the patch in i386/14437

>Description:

  identcpu.c was missing CPUID bit definitions for several AMD extended
features. It also mistakingly labeled bit 16 of the AMD features as "FCMOV"
when the AMD Processor Recognition datasheet found at
  WWW: http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
specifically identifies bit 16 as PAT (same as Pentium features bit 16).


>How-To-Repeat:
>Fix:
	
--- identcpu.c.orig	Wed Oct 20 14:30:39 1999
+++ identcpu.c	Wed Oct 20 14:37:24 1999
@@ -566,7 +566,7 @@
 			"\012APIC"	/* SMP local APIC */
 			"\013oldMTRR"
 			"\014SEP"
-			"\015MTRR"
+			"\015MTRR"	/* Memory Type Range Registers */
 			"\016PGE"	/* PG_G (global bit) support */
 			"\017MCA"
 			"\020CMOV"	/* CMOV instruction */
@@ -961,40 +961,44 @@
 static void
 print_AMD_features(u_int *regs)
 {
+	/*
+	 * Values taken from AMD Processor Recognition
+	 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
+	 */
 	do_cpuid(0x80000001, regs);
 	printf("\n  AMD Features=0x%b", regs[3] &~ cpu_feature,
 		"\020"		/* in hex */
-		"\001FPU"
-		"\002VME"
-		"\003DE"
-		"\004PSE"
-		"\005TSC"
-		"\006MSR"
-		"\007<b6>"
-		"\010MCE"
-		"\011CX8"
-		"\012<b9>"
+		"\001FPU"	/* Integral FPU */
+		"\002VME"	/* Extended VM86 mode support */
+		"\003DE"	/* Debug extensions */
+		"\004PSE"	/* 4MByte page tables */
+		"\005TSC"	/* Timestamp counter */
+		"\006MSR"	/* Machine specific registers */
+		"\007PAE"	/* Physical address extension */
+		"\010MCE"	/* Machine Check support */
+		"\011CX8"	/* CMPEXCH8 instruction */
+		"\012APIC"	/* SMP local APIC */
 		"\013<b10>"
-		"\014SYSCALL"
-		"\015<b12>"
-		"\016PGE"
-		"\017<b14>"
-		"\020ICMOV"
-		"\021FCMOV"
-		"\022<b17>"
+		"\014SYSCALL"	/* SYSENTER/SYSEXIT instructions */
+		"\015MTRR"	/* Memory Type Range Registers */		
+		"\016PGE"	/* PG_G (global bit) support */
+		"\017MCA"	/* Machine Check Architecture */
+		"\020ICMOV"	/* CMOV instruction */
+		"\021PAT"	/* Page attributes table */
+		"\022PGE36"	/* 36 bit address space support */
 		"\023<b18>"
 		"\024<b19>"
 		"\025<b20>"
 		"\026<b21>"
-		"\027<b22>"
+		"\027AMX"	/* AMD MMX Extensions */
 		"\030MMX"
-		"\031<b24>"
+		"\031FXSAVE"	/* FXSAVE/FXRSTOR */
 		"\032<b25>"
 		"\033<b26>"
 		"\034<b27>"
 		"\035<b28>"
 		"\036<b29>"
-		"\037<b30>"
+		"\0373DX"	/* 3DNow! Extensions */
 		"\0403DNow!"
 		);
 }

>Release-Note:
>Audit-Trail:
>Unformatted:


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