Date: Sun, 5 Nov 2006 06:35:20 GMT From: Sam Leffler <sam@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 109267 for review Message-ID: <200611050635.kA56ZKTT080024@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=109267 Change 109267 by sam@sam_ebb on 2006/11/05 06:35:16 merge work from sam_avila branch Affected files ... .. //depot/projects/arm/src/sys/arm/xscale/ixp425/IxNpeMicrocode.dat#1 add .. //depot/projects/arm/src/sys/arm/xscale/ixp425/avila_machdep.c#4 edit .. //depot/projects/arm/src/sys/arm/xscale/ixp425/files.ixp425#5 edit .. //depot/projects/arm/src/sys/arm/xscale/ixp425/if_npe.c#1 add .. //depot/projects/arm/src/sys/arm/xscale/ixp425/if_npereg.h#1 add .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425.c#13 edit .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_npe.c#1 add .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_npe.h#1 add .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_npevar.h#1 add .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_pci.c#15 edit .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_pci_space.c#7 edit .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_qmgr.c#1 add .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_qmgr.h#1 add .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425reg.h#3 edit Differences ... ==== //depot/projects/arm/src/sys/arm/xscale/ixp425/avila_machdep.c#4 (text+ko) ==== @@ -195,6 +195,54 @@ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + /* NPE-A Memory Space */ + { + IXP425_NPE_A_VBASE, + IXP425_NPE_A_HWBASE, + IXP425_NPE_A_SIZE, + VM_PROT_READ|VM_PROT_WRITE, + PTE_NOCACHE, + }, + /* NPE-B Memory Space */ + { + IXP425_NPE_B_VBASE, + IXP425_NPE_B_HWBASE, + IXP425_NPE_B_SIZE, + VM_PROT_READ|VM_PROT_WRITE, + PTE_NOCACHE, + }, + /* NPE-C Memory Space */ + { + IXP425_NPE_C_VBASE, + IXP425_NPE_C_HWBASE, + IXP425_NPE_C_SIZE, + VM_PROT_READ|VM_PROT_WRITE, + PTE_NOCACHE, + }, + /* MAC-A Memory Space */ + { + IXP425_MAC_A_VBASE, + IXP425_MAC_A_HWBASE, + IXP425_MAC_A_SIZE, + VM_PROT_READ|VM_PROT_WRITE, + PTE_NOCACHE, + }, + /* MAC-B Memory Space */ + { + IXP425_MAC_B_VBASE, + IXP425_MAC_B_HWBASE, + IXP425_MAC_B_SIZE, + VM_PROT_READ|VM_PROT_WRITE, + PTE_NOCACHE, + }, + /* Q-Mgr Memory Space */ + { + IXP425_QMGR_VBASE, + IXP425_QMGR_HWBASE, + IXP425_QMGR_SIZE, + VM_PROT_READ|VM_PROT_WRITE, + PTE_NOCACHE, + }, { 0, ==== //depot/projects/arm/src/sys/arm/xscale/ixp425/files.ixp425#5 (text+ko) ==== @@ -14,3 +14,26 @@ arm/xscale/ixp425/ixp425_a4x_space.c optional uart arm/xscale/ixp425/ixp425_a4x_io.S optional uart dev/uart/uart_dev_ns8250.c optional uart +# +# NPE-based Ethernet support (requires qmgr also) +# +arm/xscale/ixp425/if_npe.c optional npe +arm/xscale/ixp425/ixp425_npe.c optional npe +ixp425_npe_fw.c optional npe_fw \ + compile-with "${AWK} -f $S/tools/fw_stub.awk IxNpeMicrocode.dat:npe_fw -mnpe -c${.TARGET}" \ + no-implicit-rule before-depend local \ + clean "ixp425_npe_fw.c" +# +# NB: ld encodes the path in the binary symbols generated for the +# firmware image so link the file to the object directory to +# get known values for reference in the _fw.c file. +# +IxNpeMicrocode.fwo optional npe_fw \ + dependency "$S/arm/xscale/ixp425/IxNpeMicrocode.dat" \ + compile-with "ln -s $S/arm/xscale/ixp425/IxNpeMicrocode.dat ${.OBJDIR}; ${LD} -b binary -d -warn-common -r -d -o ${.TARGET} IxNpeMicrocode.dat" \ + no-implicit-rule \ + clean "IxNpeMicrocode.dat IxNpeMicrocode.fwo" +# +# Q-Manager support +# +arm/xscale/ixp425/ixp425_qmgr.c optional qmgr ==== //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425.c#13 (text+ko) ==== @@ -78,6 +78,7 @@ { IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, IXP425_QMGR_VBASE }, { IXP425_NPE_A_HWBASE, IXP425_NPE_A_SIZE, IXP425_NPE_A_VBASE }, { IXP425_NPE_B_HWBASE, IXP425_NPE_B_SIZE, IXP425_NPE_B_VBASE }, + { IXP425_NPE_C_HWBASE, IXP425_NPE_C_SIZE, IXP425_NPE_C_VBASE }, { IXP425_MAC_A_HWBASE, IXP425_MAC_A_SIZE, IXP425_MAC_A_VBASE }, { IXP425_MAC_B_HWBASE, IXP425_MAC_B_SIZE, IXP425_MAC_B_VBASE }, }; ==== //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_pci.c#15 (text+ko) ==== @@ -287,7 +287,6 @@ } rv = rman_reserve_resource(rmanp, start, end, count, flags, child); - device_printf(bus, "start: %#lx, end: %#lx, count: %#lx, flags: %#x, rv: %p\n", start, end, count, flags, rv); if (rv != NULL) { rman_set_rid(rv, *rid); if (type == SYS_RES_IOPORT) { ==== //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_pci_space.c#7 (text+ko) ==== @@ -295,7 +295,7 @@ u_int32_t data; data = _bs_r(v, ioh, off, 0); - return (data); + return data; } #ifdef __ARMEB__ @@ -329,7 +329,7 @@ u_int32_t data; data = _bs_r(v, ioh, off, 0); - return data; + return le32toh(data); } #endif /* __ARMEB__ */ @@ -372,7 +372,6 @@ _pci_io_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off, u_int32_t val) { - _bs_w(v, ioh, off, 0, val); } @@ -405,7 +404,7 @@ _pci_io_bs_w_4_s(void *v, bus_space_handle_t ioh, bus_size_t off, u_int32_t val) { - _bs_w(v, ioh, off, 0, val); + _bs_w(v, ioh, off, 0, htole32(val)); } #endif /* __ARMEB__ */ ==== //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425reg.h#3 (text+ko) ==== @@ -108,9 +108,9 @@ #define IXP425_INTR_OFFSET 0x00003000UL #define IXP425_GPIO_OFFSET 0x00004000UL #define IXP425_TIMER_OFFSET 0x00005000UL -#define IXP425_HSS_OFFSET 0x00006000UL /* Not User Programmable */ -#define IXP425_NPE_A_OFFSET 0x00007000UL /* Not User Programmable */ -#define IXP425_NPE_B_OFFSET 0x00008000UL /* Not User Programmable */ +#define IXP425_NPE_A_OFFSET 0x00006000UL /* Not User Programmable */ +#define IXP425_NPE_B_OFFSET 0x00007000UL /* Not User Programmable */ +#define IXP425_NPE_C_OFFSET 0x00008000UL /* Not User Programmable */ #define IXP425_MAC_A_OFFSET 0x00009000UL #define IXP425_MAC_B_OFFSET 0x0000a000UL #define IXP425_USB_OFFSET 0x0000b000UL @@ -216,9 +216,9 @@ #define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */ #define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */ #define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */ -#define IXP425_INT_NPE_B 2 /* Ethernet NPE B */ -#define IXP425_INT_NPE_A 1 /* Ethernet NPE A */ -#define IXP425_INT_HSS 0 /* WAN/HSS NPE */ +#define IXP425_INT_NPE_C 2 /* NPE C */ +#define IXP425_INT_NPE_B 1 /* NPE B */ +#define IXP425_INT_NPE_A 0 /* NPE A */ /* * software interrupt @@ -291,6 +291,7 @@ #define EXP_TIMING_CS7_OFFSET 0x001c #define EXP_CNFG0_OFFSET 0x0020 #define EXP_CNFG1_OFFSET 0x0024 +#define EXP_FCTRL_OFFSET 0x0028 #define IXP425_EXP_RECOVERY_SHIFT 16 #define IXP425_EXP_HOLD_SHIFT 20 @@ -305,7 +306,7 @@ #define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT) #define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_ADDR_SHIFT) -// EXP_CSn bits +/* EXP_CSn bits */ #define EXP_BYTE_EN (1 << 0) #define EXP_WR_EN (1 << 1) #define EXP_SPLT_EN (1 << 3) @@ -332,17 +333,34 @@ #define EXP_CYC_MOTO (1 << 14) #define EXP_CYC_HPI (2 << 14) -// EXP_CNFG0 bits +/* EXP_CNFG0 bits */ #define EXP_CNFG0_8BIT (1 << 0) #define EXP_CNFG0_PCI_HOST (1 << 1) #define EXP_CNFG0_PCI_ARB (1 << 2) #define EXP_CNFG0_PCI_66MHZ (1 << 4) #define EXP_CNFG0_MEM_MAP (1 << 31) -// EXP_CNFG1 bits +/* EXP_CNFG1 bits */ #define EXP_CNFG1_SW_INT0 (1 << 0) #define EXP_CNFG1_SW_INT1 (1 << 1) +#define EXP_FCTRL_RCOMP (1<<0) +#define EXP_FCTRL_USB (1<<1) +#define EXP_FCTRL_HASH (1<<2) +#define EXP_FCTRL_AES (1<<3) +#define EXP_FCTRL_DES (1<<4) +#define EXP_FCTRL_HDLC (1<<5) +#define EXP_FCTRL_AAL (1<<6) +#define EXP_FCTRL_HSS (1<<7) +#define EXP_FCTRL_UTOPIA (1<<8) +#define EXP_FCTRL_ETH0 (1<<9) +#define EXP_FCTRL_ETH1 (1<<10) +#define EXP_FCTRL_NPEA (1<<11) +#define EXP_FCTRL_NPEB (1<<12) +#define EXP_FCTRL_NPEC (1<<13) +#define EXP_FCTRL_PCI (1<<14) +/* XXX more stuff we don't care about */ + /* * PCI */ @@ -500,8 +518,7 @@ */ #define IXP425_QMGR_HWBASE 0x60000000UL #define IXP425_QMGR_VBASE (IXP425_PCI_VBASE + IXP425_PCI_SIZE) -/* NB: really only 0x4000 */ -#define IXP425_QMGR_SIZE IXP425_IO_SIZE +#define IXP425_QMGR_SIZE 0x4000 /* * Network Processing Engines (NPE's) and associated Ethernet MAC's.
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