Date: Sun, 9 Jul 2006 11:53:51 GMT From: "Wojciech A. Koszek" <wkoszek@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 101093 for review Message-ID: <200607091153.k69BrpGu092431@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=101093 Change 101093 by wkoszek@wkoszek_laptop on 2006/07/09 11:53:14 Bring my chages from yesterday session cpu.c: - Body of the mips_wtf(struct wtf *wtf) is disabled for now. We distinguish which CPU is used, and we fill '*wtf' with proper values. For now, fill struct wft members with dummy values. - Add a comment about possible code path which happens after mips_init() is run. - Disable mips_icache_sync_all() and mips_dcache_wbinv_all(), and comment this change. machdep.c: - Add comments related with init_param2(), mips_cpu_init() and pmap_bootstrap() calls. - Disable block responsible for calling proc_linkup(), pcpu_init() and kdb_init(). - Add a comment related with function flow after locore.S. - Move MALTA specific values out of the plaform_start() and make them global for machdep.c. This is ugly, and should we moved under src/sys/mips/mips4k/malta/... hierarchy, but this code is very useful for debugging in GXemul. tlb.c: - Add a comment related with xcontext, similar to bms@'s ones from cpufunc.h - Partially enable tlb_update(). Right now we don't have MIPS_HI_ENTRY() macro working properly. - Partially enable tlb_invalidate_page(). The same here - we don't have MIPS_HI_ENTRY() macro working properly. Affected files ... .. //depot/projects/mips2/src/sys/mips/mips/cpu.c#4 edit .. //depot/projects/mips2/src/sys/mips/mips/machdep.c#10 edit .. //depot/projects/mips2/src/sys/mips/mips/tlb.c#3 edit Differences ... ==== //depot/projects/mips2/src/sys/mips/mips/cpu.c#4 (text+ko) ==== @@ -132,16 +132,22 @@ static void mips_wtf(struct wtf *wtf) { + + /* + * XXXMIPS: Comment it for now, since I haven't get to + * CPU-specifications and differences between them. Bring sample + * values here. + */ + wtf->wtf_class = MIPS_R4000; + wtf->wtf_type = "XZ"; + wtf->wtf_ntlbs = 2; /* XX Find the right value. */ + wtf->wtf_fpu = "YC"; +#if 0 unsigned long cpu_class; const char *cpu_type; unsigned long cpu_ntlbs; const char *cpu_fpu; - cpu_class = 0; - cpu_type = NULL; - cpu_ntlbs = 0; - cpu_fpu = NULL; - switch (MIPS_PRID_IMPL(cpu_id)) { case MIPS_R4000: cpu_class = MIPS_R4000; @@ -175,8 +181,23 @@ printf("Unknown CPU cpu_id=%x\n", cpu_id); printf("Unknown FPU fpu_id=%x\n", fpu_id); panic("Please send this output to freebsd-mips@freeebsd.org"); +#endif } +/* + * Possible code path + * ------------------ + * mips_init(): (from machdep.c) + * | + * +- mips_cpu_init(): (this file -- cpu.c) + * | + * +- mips_wtf() (this file -- cpu.c) ok + * +- mips_config_cache() (this file -- cpu.c) stub + * +- tlb_invalidate_all() (tlb.c) + * +- mips_vector_init() (this file -- cpu.c) + * +- mips_icache_sync_all() (cache.c ?) XX + * +- mips_dcache_wbinv_all() (cache.c ?) XX + */ void mips_cpu_init(void) { @@ -189,8 +210,15 @@ mips_config_cache(); tlb_invalidate_all(); mips_vector_init(); + /* + * XXXMIPS: Leave touching cache until we decide, how we're going to + * manage differences between icache and dcache handling between + * processors. + */ +#if 0 mips_icache_sync_all(); mips_dcache_wbinv_all(); +#endif } void ==== //depot/projects/mips2/src/sys/mips/mips/machdep.c#10 (text+ko) ==== @@ -37,6 +37,7 @@ #include <sys/buf.h> #include <sys/bus.h> #include <sys/cpu.h> +#include <sys/cons.h> #include <sys/ucontext.h> #include <sys/proc.h> #include <sys/kdb.h> @@ -89,10 +90,24 @@ void mips_init(void) { + /* + * XXXMIPS: This one is called from subr_param.c. + */ init_param2(physmem); + /* + * XXXMIPS: This one lies in cpu.c. + */ mips_cpu_init(); + /* + * XXXMIPS: This is from pmap.c. + */ pmap_bootstrap(); + /* + * XXXMIPS: Change this once I'll make sure pagetables are working + * correctly. + */ +#if 0 proc_linkup(&proc0, &ksegrp0, &thread0); thread0.td_kstack = kstack0; pcpu_init(pcpup, 0, sizeof(struct pcpu)); @@ -103,6 +118,7 @@ #ifdef DDB kdb_init(); #endif +#endif } void @@ -295,11 +311,6 @@ } -void -platform_start(int argc, char **argv) -{ - volatile uint32_t * dest_ch; - #define MALTA_FPGA_BASE 0x1f000000 /* FPGA: */ #define MALTA_FPGA_SIZE 0x00c00000 /* 12 MByte */ @@ -315,6 +326,26 @@ #define MALTA_ASCIIPOS6 0x30 #define MALTA_ASCIIPOS7 0x38 +/* + * + * Existing code path + * ------------------ + * locore.S: + * | + * +->platform_start(): (here -- machdep.c) + * | + * +-MALTA_PUTCHAR() (macros to get malta LCD working) + * +-mips_init(): (here -- machdep.c) + * | + * +-init_param2() (subr_param.c) + * +-mips_cpu_init() (cpu.c) + * +-pmap_bootstrap() (pmap.c) + */ +void +platform_start(int argc, char **argv) +{ + volatile uint32_t * dest_ch; + #define MALTA_PUTCHAR(pos, ch) \ dest_ch = (uint32_t *) \ MIPS_PHYS_TO_KSEG0(MALTA_ASCII_BASE + MALTA_ASCIIPOS ## pos); \ @@ -328,7 +359,8 @@ MALTA_PUTCHAR(5, 'S'); MALTA_PUTCHAR(6, 'D'); - memset((char *)MIPS_PHYS_TO_KSEG0(0x1fc00500 + 0x04), 'x', 10); + mips_init(); + cninit(); } void setPQL2(int *const size, int *const ways); ==== //depot/projects/mips2/src/sys/mips/mips/tlb.c#3 (text+ko) ==== @@ -115,6 +115,9 @@ */ mips_wr_wired(1); + /* + * XXXMIPS: Does xcontext exist on mips32? + */ #if 0 /* * Set up page table. @@ -172,17 +175,24 @@ tlb_remove_pages(pmap, va, eva - va); } +/* + * XXXMIPS: Check this one. + */ void tlb_update(vm_offset_t va, pt_entry_t pte0, pt_entry_t pte1) { u_long ehi; int i; - ehi = 0; - i = 0; + va &= ~PAGE_MASK; + /* + * XXXMIPS: This will probably mean bringing stuff from NetBSD, as + * juli's code has offsets and sizes for mips64. + */ #if 0 - va &= ~PAGE_MASK; ehi = MIPS_HI_ENTRY(va, /*asid*/0); +#endif + ehi = 0; mips_wr_entryhi(ehi); mips_tlbp(); i = mips_rd_index(); @@ -193,7 +203,6 @@ mips_tlbwr(); else mips_tlbwi(); -#endif } void @@ -226,24 +235,30 @@ mips_tlbwi(); } +/* + * XXXMIPS: Check this one. + */ void tlb_invalidate_page(vm_offset_t va) { u_long ehi; int i; - ehi = 0; - i = 0; + va &= ~PAGE_MASK; + /* + * XXXMIPS: This will probably mean bringing stuff from NetBSD, as + * juli's code has offsets and sizes for mips64. + */ #if 0 - va &= ~PAGE_MASK; ehi = MIPS_HI_ENTRY(va, /*asid*/0); +#endif + ehi = 0; mips_wr_entryhi(ehi); mips_tlbp(); i = mips_rd_index(); if (i >= 0) tlb_invalidate_one(i); mips_dcache_wbinv_range_index(va, PAGE_SIZE); -#endif } /*
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