Date: Mon, 5 Sep 2011 10:45:29 +0000 (UTC) From: "Jayachandran C." <jchandra@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r225394 - in head/sys/mips: conf nlm nlm/hal Message-ID: <201109051045.p85AjTeK034574@svn.freebsd.org>
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Author: jchandra Date: Mon Sep 5 10:45:29 2011 New Revision: 225394 URL: http://svn.freebsd.org/changeset/base/225394 Log: MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett Added: head/sys/mips/nlm/bus_space_rmi_pci.c (contents, props changed) head/sys/mips/nlm/hal/haldefs.h (contents, props changed) head/sys/mips/nlm/hal/pcibus.h (contents, props changed) head/sys/mips/nlm/hal/usb.h (contents, props changed) head/sys/mips/nlm/intern_dev.c (contents, props changed) head/sys/mips/nlm/uart_cpu_xlp.c (contents, props changed) head/sys/mips/nlm/uart_pci_xlp.c (contents, props changed) head/sys/mips/nlm/usb_init.c (contents, props changed) head/sys/mips/nlm/xlp_pci.c (contents, props changed) Deleted: head/sys/mips/nlm/hal/cop0.h head/sys/mips/nlm/hal/mmio.h head/sys/mips/nlm/iodi.c head/sys/mips/nlm/uart_cpu_mips_xlp.c Modified: head/sys/mips/conf/XLP head/sys/mips/conf/XLP64 head/sys/mips/conf/XLPN32 head/sys/mips/nlm/board.c head/sys/mips/nlm/board.h head/sys/mips/nlm/bus_space_rmi.c head/sys/mips/nlm/clock.h head/sys/mips/nlm/cms.c head/sys/mips/nlm/files.xlp head/sys/mips/nlm/hal/bridge.h head/sys/mips/nlm/hal/cop2.h head/sys/mips/nlm/hal/cpucontrol.h head/sys/mips/nlm/hal/fmn.c head/sys/mips/nlm/hal/fmn.h head/sys/mips/nlm/hal/iomap.h head/sys/mips/nlm/hal/mips-extns.h head/sys/mips/nlm/hal/mmu.h head/sys/mips/nlm/hal/pic.h head/sys/mips/nlm/hal/sys.h head/sys/mips/nlm/hal/uart.h head/sys/mips/nlm/interrupt.h head/sys/mips/nlm/intr_machdep.c head/sys/mips/nlm/mpreset.S head/sys/mips/nlm/msgring.h head/sys/mips/nlm/uart_bus_xlp_iodi.c head/sys/mips/nlm/xlp.h head/sys/mips/nlm/xlp_machdep.c Modified: head/sys/mips/conf/XLP ============================================================================== --- head/sys/mips/conf/XLP Mon Sep 5 10:09:53 2011 (r225393) +++ head/sys/mips/conf/XLP Mon Sep 5 10:45:29 2011 (r225394) @@ -36,7 +36,7 @@ options SCHED_ULE # ULE scheduler options SMP options PREEMPTION # Enable kernel thread preemption #options FULL_PREEMPTION # Enable kernel thread preemption -options MAXCPU=128 # XLP can probe 128 CPUs +#options MAXCPU=128 # XLP can probe 128 CPUs options INET # InterNETworking options INET6 # IPv6 communications protocols options FFS # Berkeley Fast Filesystem @@ -89,6 +89,7 @@ device bpf # UART device uart +device pci # Network device ether Modified: head/sys/mips/conf/XLP64 ============================================================================== --- head/sys/mips/conf/XLP64 Mon Sep 5 10:09:53 2011 (r225393) +++ head/sys/mips/conf/XLP64 Mon Sep 5 10:45:29 2011 (r225394) @@ -21,7 +21,7 @@ machine mips mips64eb ident XLP64 options ISA_MIPS64 -makeoptions ARCH_FLAGS="-march=mips64 -mabi=64" +makeoptions ARCH_FLAGS="-march=mips64r2 -mabi=64" makeoptions KERNLOADADDR=0xffffffff80100000 include "../nlm/std.xlp" @@ -38,7 +38,7 @@ options SCHED_ULE # ULE scheduler options SMP options PREEMPTION # Enable kernel thread preemption #options FULL_PREEMPTION # Enable kernel thread preemption -options MAXCPU=128 # XLP can probe 128 CPUs +#options MAXCPU=128 # XLP can probe 128 CPUs options INET # InterNETworking options INET6 # IPv6 communications protocols options FFS # Berkeley Fast Filesystem @@ -91,6 +91,7 @@ device bpf # UART device uart +device pci # Network device ether Modified: head/sys/mips/conf/XLPN32 ============================================================================== --- head/sys/mips/conf/XLPN32 Mon Sep 5 10:09:53 2011 (r225393) +++ head/sys/mips/conf/XLPN32 Mon Sep 5 10:45:29 2011 (r225394) @@ -37,7 +37,7 @@ options SCHED_ULE # ULE scheduler options SMP options PREEMPTION # Enable kernel thread preemption #options FULL_PREEMPTION # Enable kernel thread preemption -options MAXCPU=128 # XLP can probe 128 CPUs +#options MAXCPU=128 # XLP can probe 128 CPUs options INET # InterNETworking options INET6 # IPv6 communications protocols options FFS # Berkeley Fast Filesystem @@ -90,6 +90,7 @@ device bpf # UART device uart +device pci # Network device ether Modified: head/sys/mips/nlm/board.c ============================================================================== --- head/sys/mips/nlm/board.c Mon Sep 5 10:09:53 2011 (r225393) +++ head/sys/mips/nlm/board.c Mon Sep 5 10:45:29 2011 (r225394) @@ -29,7 +29,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); - #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -38,7 +37,7 @@ __FBSDID("$FreeBSD$"); #include <sys/mutex.h> #include <mips/nlm/hal/mips-extns.h> -#include <mips/nlm/hal/mmio.h> +#include <mips/nlm/hal/haldefs.h> #include <mips/nlm/hal/iomap.h> #include <mips/nlm/hal/fmn.h> #include <mips/nlm/hal/pic.h> Modified: head/sys/mips/nlm/board.h ============================================================================== --- head/sys/mips/nlm/board.h Mon Sep 5 10:09:53 2011 (r225393) +++ head/sys/mips/nlm/board.h Mon Sep 5 10:45:29 2011 (r225394) @@ -25,8 +25,9 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * + * NETLOGIC_BSD * $FreeBSD$ - * NETLOGIC_BSD */ + */ #ifndef __NLM_BOARD_H__ #define __NLM_BOARD_H__ Modified: head/sys/mips/nlm/bus_space_rmi.c ============================================================================== --- head/sys/mips/nlm/bus_space_rmi.c Mon Sep 5 10:09:53 2011 (r225393) +++ head/sys/mips/nlm/bus_space_rmi.c Mon Sep 5 10:45:29 2011 (r225394) @@ -401,14 +401,14 @@ static u_int8_t rmi_bus_space_read_1(void *tag, bus_space_handle_t handle, bus_size_t offset) { - return (u_int8_t) (*(volatile u_int32_t *)(handle + offset)); + return (u_int8_t) (*(volatile u_int8_t *)(handle + offset)); } static u_int16_t rmi_bus_space_read_2(void *tag, bus_space_handle_t handle, bus_size_t offset) { - return (u_int16_t)(*(volatile u_int32_t *)(handle + offset)); + return (u_int16_t)(*(volatile u_int16_t *)(handle + offset)); } static u_int32_t @@ -453,14 +453,14 @@ static void rmi_bus_space_write_1(void *tag, bus_space_handle_t handle, bus_size_t offset, u_int8_t value) { - *(volatile u_int32_t *)(handle + offset) = (u_int32_t)value; + *(volatile u_int8_t *)(handle + offset) = value; } static void rmi_bus_space_write_2(void *tag, bus_space_handle_t handle, bus_size_t offset, u_int16_t value) { - *(volatile u_int32_t *)(handle + offset) = (u_int32_t)value; + *(volatile u_int16_t *)(handle + offset) = value; } static void Added: head/sys/mips/nlm/bus_space_rmi_pci.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/nlm/bus_space_rmi_pci.c Mon Sep 5 10:45:29 2011 (r225394) @@ -0,0 +1,768 @@ +/*- + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * NETLOGIC_BSD */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/endian.h> +#include <sys/malloc.h> +#include <sys/ktr.h> + +#include <vm/vm.h> +#include <vm/pmap.h> +#include <vm/vm_kern.h> +#include <vm/vm_extern.h> + +#include <machine/bus.h> +#include <machine/cache.h> + +static int +rmi_pci_bus_space_map(void *t, bus_addr_t addr, + bus_size_t size, int flags, + bus_space_handle_t * bshp); + +static void +rmi_pci_bus_space_unmap(void *t, bus_space_handle_t bsh, + bus_size_t size); + +static int +rmi_pci_bus_space_subregion(void *t, + bus_space_handle_t bsh, + bus_size_t offset, bus_size_t size, + bus_space_handle_t * nbshp); + +static u_int8_t +rmi_pci_bus_space_read_1(void *t, + bus_space_handle_t handle, + bus_size_t offset); + +static u_int16_t +rmi_pci_bus_space_read_2(void *t, + bus_space_handle_t handle, + bus_size_t offset); + +static u_int32_t +rmi_pci_bus_space_read_4(void *t, + bus_space_handle_t handle, + bus_size_t offset); + +static void +rmi_pci_bus_space_read_multi_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_region_1(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_region_4(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int32_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int8_t value); + +static void +rmi_pci_bus_space_write_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int16_t value); + +static void +rmi_pci_bus_space_write_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int32_t value); + +static void +rmi_pci_bus_space_write_multi_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_multi_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_multi_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int32_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_region_4(void *t, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int32_t * addr, + size_t count); + + +static void +rmi_pci_bus_space_set_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value, + size_t count); +static void +rmi_pci_bus_space_set_region_4(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int32_t value, + size_t count); + +static void +rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, + bus_size_t offset __unused, bus_size_t len __unused, int flags); + +static void +rmi_pci_bus_space_copy_region_2(void *t, + bus_space_handle_t bsh1, + bus_size_t off1, + bus_space_handle_t bsh2, + bus_size_t off2, size_t count); + +u_int8_t +rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle, + bus_size_t offset); + +static u_int16_t +rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset); + +static u_int32_t +rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset); +static void +rmi_pci_bus_space_read_multi_stream_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_stream_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_stream_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, + size_t count); + +void +rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t value); +static void +rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int16_t value); + +static void +rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int32_t value); + +static void +rmi_pci_bus_space_write_multi_stream_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int8_t * addr, + size_t count); +static void +rmi_pci_bus_space_write_multi_stream_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_multi_stream_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int32_t * addr, + size_t count); + +#define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__) + +static struct bus_space local_rmi_pci_bus_space = { + /* cookie */ + (void *)0, + + /* mapping/unmapping */ + rmi_pci_bus_space_map, + rmi_pci_bus_space_unmap, + rmi_pci_bus_space_subregion, + + /* allocation/deallocation */ + NULL, + NULL, + + /* barrier */ + rmi_pci_bus_space_barrier, + + /* read (single) */ + rmi_pci_bus_space_read_1, + rmi_pci_bus_space_read_2, + rmi_pci_bus_space_read_4, + NULL, + + /* read multiple */ + rmi_pci_bus_space_read_multi_1, + rmi_pci_bus_space_read_multi_2, + rmi_pci_bus_space_read_multi_4, + NULL, + + /* read region */ + rmi_pci_bus_space_read_region_1, + rmi_pci_bus_space_read_region_2, + rmi_pci_bus_space_read_region_4, + NULL, + + /* write (single) */ + rmi_pci_bus_space_write_1, + rmi_pci_bus_space_write_2, + rmi_pci_bus_space_write_4, + NULL, + + /* write multiple */ + rmi_pci_bus_space_write_multi_1, + rmi_pci_bus_space_write_multi_2, + rmi_pci_bus_space_write_multi_4, + NULL, + + /* write region */ + NULL, + rmi_pci_bus_space_write_region_2, + rmi_pci_bus_space_write_region_4, + NULL, + + /* set multiple */ + NULL, + NULL, + NULL, + NULL, + + /* set region */ + NULL, + rmi_pci_bus_space_set_region_2, + rmi_pci_bus_space_set_region_4, + NULL, + + /* copy */ + NULL, + rmi_pci_bus_space_copy_region_2, + NULL, + NULL, + + /* read (single) stream */ + rmi_pci_bus_space_read_stream_1, + rmi_pci_bus_space_read_stream_2, + rmi_pci_bus_space_read_stream_4, + NULL, + + /* read multiple stream */ + rmi_pci_bus_space_read_multi_stream_1, + rmi_pci_bus_space_read_multi_stream_2, + rmi_pci_bus_space_read_multi_stream_4, + NULL, + + /* read region stream */ + rmi_pci_bus_space_read_region_1, + rmi_pci_bus_space_read_region_2, + rmi_pci_bus_space_read_region_4, + NULL, + + /* write (single) stream */ + rmi_pci_bus_space_write_stream_1, + rmi_pci_bus_space_write_stream_2, + rmi_pci_bus_space_write_stream_4, + NULL, + + /* write multiple stream */ + rmi_pci_bus_space_write_multi_stream_1, + rmi_pci_bus_space_write_multi_stream_2, + rmi_pci_bus_space_write_multi_stream_4, + NULL, + + /* write region stream */ + NULL, + rmi_pci_bus_space_write_region_2, + rmi_pci_bus_space_write_region_4, + NULL, +}; + +/* generic bus_space tag */ +bus_space_tag_t rmi_pci_bus_space = &local_rmi_pci_bus_space; + +/* + * Map a region of device bus space into CPU virtual address space. + */ +static int +rmi_pci_bus_space_map(void *t __unused, bus_addr_t addr, + bus_size_t size __unused, int flags __unused, + bus_space_handle_t * bshp) +{ + *bshp = addr; + return (0); +} + +/* + * Unmap a region of device bus space. + */ +static void +rmi_pci_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused, + bus_size_t size __unused) +{ +} + +/* + * Get a new handle for a subregion of an already-mapped area of bus space. + */ + +static int +rmi_pci_bus_space_subregion(void *t __unused, bus_space_handle_t bsh, + bus_size_t offset, bus_size_t size __unused, + bus_space_handle_t * nbshp) +{ + *nbshp = bsh + offset; + return (0); +} + +/* + * Read a 1, 2, 4, or 8 byte quantity from bus space + * described by tag/handle/offset. + */ + +static u_int8_t +rmi_pci_bus_space_read_1(void *tag, bus_space_handle_t handle, + bus_size_t offset) +{ + return (u_int8_t) (*(volatile u_int8_t *)(handle + offset)); +} + +static u_int16_t +rmi_pci_bus_space_read_2(void *tag, bus_space_handle_t handle, + bus_size_t offset) +{ + u_int16_t value; + + value = *(volatile u_int16_t *)(handle + offset); + return bswap16(value); +} + +static u_int32_t +rmi_pci_bus_space_read_4(void *tag, bus_space_handle_t handle, + bus_size_t offset) +{ + uint32_t value; + + value = *(volatile u_int32_t *)(handle + offset); + return bswap32(value); +} + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle/offset and copy into buffer provided. + */ +static void +rmi_pci_bus_space_read_multi_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, size_t count) +{ + while (count--) { + *addr = *(volatile u_int8_t *)(handle + offset); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, size_t count) +{ + + while (count--) { + *addr = *(volatile u_int16_t *)(handle + offset); + *addr = bswap16(*addr); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, size_t count) +{ + + while (count--) { + *addr = *(volatile u_int32_t *)(handle + offset); + *addr = bswap32(*addr); + addr++; + } +} + +/* + * Write the 1, 2, 4, or 8 byte value `value' to bus space + * described by tag/handle/offset. + */ + +static void +rmi_pci_bus_space_write_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int8_t value) +{ + mips_sync(); + *(volatile u_int8_t *)(handle + offset) = value; +} + +static void +rmi_pci_bus_space_write_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int16_t value) +{ + mips_sync(); + *(volatile u_int16_t *)(handle + offset) = bswap16(value); +} + + +static void +rmi_pci_bus_space_write_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int32_t value) +{ + mips_sync(); + *(volatile u_int32_t *)(handle + offset) = bswap32(value); +} + +/* + * Write `count' 1, 2, 4, or 8 byte quantities from the buffer + * provided to bus space described by tag/handle/offset. + */ + + +static void +rmi_pci_bus_space_write_multi_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int8_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int8_t *)(handle + offset)) = *addr; + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int16_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int16_t *)(handle + offset)) = bswap16(*addr); + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int32_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int32_t *)(handle + offset)) = bswap32(*addr); + addr++; + } +} + +/* + * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described + * by tag/handle starting at `offset'. + */ + +static void +rmi_pci_bus_space_set_region_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + for (; count != 0; count--, addr += 2) + (*(volatile u_int16_t *)(addr)) = value; +} + +static void +rmi_pci_bus_space_set_region_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + for (; count != 0; count--, addr += 4) + (*(volatile u_int32_t *)(addr)) = value; +} + + +/* + * Copy `count' 1, 2, 4, or 8 byte values from bus space starting + * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. + */ +static void +rmi_pci_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, + bus_size_t off2, size_t count) +{ + TODO(); +} + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle/offset and copy into buffer provided. + */ + +u_int8_t +rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + + return *((volatile u_int8_t *)(handle + offset)); +} + + +static u_int16_t +rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + return *(volatile u_int16_t *)(handle + offset); +} + + +static u_int32_t +rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + return (*(volatile u_int32_t *)(handle + offset)); +} + + +static void +rmi_pci_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, size_t count) +{ + while (count--) { + *addr = (*(volatile u_int8_t *)(handle + offset)); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, size_t count) +{ + while (count--) { + *addr = (*(volatile u_int16_t *)(handle + offset)); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, size_t count) +{ + while (count--) { + *addr = (*(volatile u_int32_t *)(handle + offset)); + addr++; + } +} + + + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle and starting at `offset' and copy into + * buffer provided. + */ +void +rmi_pci_bus_space_read_region_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = (*(volatile u_int8_t *)(baddr)); + baddr += 1; + } +} + +void +rmi_pci_bus_space_read_region_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = (*(volatile u_int16_t *)(baddr)); + baddr += 2; + } +} + +void +rmi_pci_bus_space_read_region_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = (*(volatile u_int32_t *)(baddr)); + baddr += 4; + } +} + + +void +rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int8_t value) +{ + mips_sync(); + *(volatile u_int8_t *)(handle + offset) = value; +} + +static void +rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int16_t value) +{ + mips_sync(); + *(volatile u_int16_t *)(handle + offset) = value; +} + + +static void +rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int32_t value) +{ + mips_sync(); + *(volatile u_int32_t *)(handle + offset) = value; +} + + +static void +rmi_pci_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int8_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int8_t *)(handle + offset)) = *addr; + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int16_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int16_t *)(handle + offset)) = *addr; + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int32_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int32_t *)(handle + offset)) = *addr; + addr++; + } +} + +void +rmi_pci_bus_space_write_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int16_t * addr, + size_t count) +{ + bus_addr_t baddr = (bus_addr_t) bsh + offset; + + while (count--) { + (*(volatile u_int16_t *)(baddr)) = *addr; + addr++; + baddr += 2; + } +} + +void +rmi_pci_bus_space_write_region_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, const u_int32_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + (*(volatile u_int32_t *)(baddr)) = *addr; + addr++; + baddr += 4; + } +} + +static void +rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, + bus_size_t offset __unused, bus_size_t len __unused, int flags) +{ + +} Modified: head/sys/mips/nlm/clock.h ============================================================================== --- head/sys/mips/nlm/clock.h Mon Sep 5 10:09:53 2011 (r225393) +++ head/sys/mips/nlm/clock.h Mon Sep 5 10:45:29 2011 (r225394) @@ -25,8 +25,9 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * + * NETLOGIC_BSD * $FreeBSD$ - * NETLOGIC_BSD */ + */ #ifndef _RMI_CLOCK_H_ #define _RMI_CLOCK_H_ Modified: head/sys/mips/nlm/cms.c ============================================================================== --- head/sys/mips/nlm/cms.c Mon Sep 5 10:09:53 2011 (r225393) +++ head/sys/mips/nlm/cms.c Mon Sep 5 10:45:29 2011 (r225394) @@ -56,9 +56,8 @@ __FBSDID("$FreeBSD$"); #include <machine/intr_machdep.h> #include <mips/nlm/hal/mips-extns.h> -#include <mips/nlm/hal/mmio.h> +#include <mips/nlm/hal/haldefs.h> #include <mips/nlm/hal/iomap.h> -#include <mips/nlm/hal/cop0.h> #include <mips/nlm/hal/cop2.h> #include <mips/nlm/hal/fmn.h> #include <mips/nlm/hal/pic.h> @@ -108,7 +107,7 @@ xlp_msgring_config(void) int i; /* TODO: Add other nodes */ - xlp_cms_base = nlm_regbase_cms(0); + xlp_cms_base = nlm_get_cms_regbase(0); mtx_init(&msgmap_lock, "msgring", NULL, MTX_SPIN); if (xlp_threads_per_core < xlp_msg_threads_per_core) @@ -147,62 +146,58 @@ xlp_msgring_iodi_config(void) void nlm_cms_credit_setup(int credit) { - int src, qid, i; + int src, qid, i; #if 0 - /* there are a total of 18 src stations on XLP. */ + /* there are a total of 18 src stations on XLP. */ printf("Setting up CMS credits!\n"); - for(src=0; src<18; src++) { - for(qid=0; qid<1024; qid++) { - nlm_cms_setup_credits(xlp_cms_base, qid, src, credit); - } - } + for (src=0; src<18; src++) { + for(qid=0; qid<1024; qid++) { + nlm_cms_setup_credits(xlp_cms_base, qid, src, credit); + } + } #endif printf("Setting up CMS credits!\n"); /* CPU Credits */ - for(i = 1; i < 8; i++) { + for (i = 1; i < 8; i++) { src = (i << 4); - for(qid = 0; qid < 1024; qid++) { - nlm_cms_setup_credits(xlp_cms_base, qid, src, credit); - } - } + for (qid = 0; qid < 1024; qid++) + nlm_cms_setup_credits(xlp_cms_base, qid, src, credit); + } /* PCIE Credits */ - for(i = 0; i < 4; i++) { + for(i = 0; i < 4; i++) { src = (256 + (i * 2)); - for(qid = 0; qid < 1024; qid++) { - nlm_cms_setup_credits(xlp_cms_base, qid, src, credit); - } - } + for(qid = 0; qid < 1024; qid++) + nlm_cms_setup_credits(xlp_cms_base, qid, src, credit); + } /* DTE Credits */ src = 264; - for(qid = 0; qid < 1024; qid++) { - nlm_cms_setup_credits(xlp_cms_base, qid, src, credit); - } + for (qid = 0; qid < 1024; qid++) + nlm_cms_setup_credits(xlp_cms_base, qid, src, credit); /* RSA Credits */ src = 272; - for(qid = 0; qid < 1024; qid++) { - nlm_cms_setup_credits(xlp_cms_base, qid, src, credit); - } + for (qid = 0; qid < 1024; qid++) + nlm_cms_setup_credits(xlp_cms_base, qid, src, credit); + *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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