Date: Thu, 22 Feb 2018 23:18:46 +0000 (UTC) From: Ravi Pokala <rpokala@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r329843 - in head: share/man/man4 sys/conf sys/dev/jedec_dimm sys/modules/i2c sys/modules/i2c/jedec_dimm Message-ID: <201802222318.w1MNIknL007063@repo.freebsd.org>
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Author: rpokala Date: Thu Feb 22 23:18:46 2018 New Revision: 329843 URL: https://svnweb.freebsd.org/changeset/base/329843 Log: jedec_dimm(4): report asset info and temperatures for DDR3 and DDR4 DIMMs A super-set of the functionality of jedec_ts(4). jedec_dimm(4) reports asset information (Part Number, Serial Number) encoded in the "Serial Presence Detect" (SPD) data on JEDEC DDR3 and DDR4 DIMMs. It also calculates and reports the memory capacity of the DIMM, in megabytes. If the DIMM includes a "Thermal Sensor On DIMM" (TSOD), the temperature is also reported. Reviewed by: cem MFC after: 1 week Relnotes: yes Sponsored by: Panasas Differential Revision: https://reviews.freebsd.org/D14392 Discussed with: avg, cem Tested by: avg, cem (previous version, no semantic changes) Added: head/share/man/man4/jedec_dimm.4 (contents, props changed) head/sys/dev/jedec_dimm/ head/sys/dev/jedec_dimm/jedec_dimm.c (contents, props changed) head/sys/dev/jedec_dimm/jedec_dimm.h (contents, props changed) head/sys/modules/i2c/jedec_dimm/ head/sys/modules/i2c/jedec_dimm/Makefile (contents, props changed) Modified: head/share/man/man4/Makefile head/sys/conf/NOTES head/sys/conf/files head/sys/modules/i2c/Makefile Modified: head/share/man/man4/Makefile ============================================================================== --- head/share/man/man4/Makefile Thu Feb 22 23:06:39 2018 (r329842) +++ head/share/man/man4/Makefile Thu Feb 22 23:18:46 2018 (r329843) @@ -248,6 +248,7 @@ MAN= aac.4 \ ixgbe.4 \ ixl.4 \ ixlv.4 \ + jedec_dimm.4 \ jedec_ts.4 \ jme.4 \ joy.4 \ Added: head/share/man/man4/jedec_dimm.4 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/share/man/man4/jedec_dimm.4 Thu Feb 22 23:18:46 2018 (r329843) @@ -0,0 +1,240 @@ +.\" +.\" SPDX-License-Identifier: BSD-2-Clause-FreeBSD +.\" +.\" Copyright (c) 2016 Andriy Gapon <avg@FreeBSD.org> +.\" Copyright (c) 2018 Ravi Pokala <rpokala@freebsd.org> +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd February 22, 2018 +.Dt JEDEC_DIMM 4 +.Os +.Sh NAME +.Nm jedec_dimm +.Nd report asset information and temperatures for JEDEC DDR3 / DDR4 DIMMs +.Sh SYNOPSIS +.Bd -ragged -offset indent +.Cd "device jedec_dimm" +.Cd "device smbus" +.Ed +.Pp +Alternatively, to load the driver as a module at boot time, place the following +line in +.Xr loader.conf 5 : +.Bd -literal -offset indent +jedec_dimm_load="YES" +.Ed +.Pp +Addressing information must be manually specified in +.Pa /boot/device.hints : +.Bd -literal -offset indent +.Cd hint.jedec_dimm.0.at="smbus0" +.Cd hint.jedec_dimm.0.addr="0xa0" +.Cd hint.jedec_dimm.0.slotid="Silkscreen" +.Ed +.Sh DESCRIPTION +The +.Nm +driver reports asset information (Part Number, Serial Number) encoded in the +.Dq Serial Presence Detect +(SPD) data on JEDEC DDR3 and DDR4 DIMMs. +It also calculates and reports the memory capacity of the DIMM, in megabytes. +If the DIMM includes a +.Dq Thermal Sensor On DIMM +(TSOD), the temperature is also reported. +.Pp +The +.Nm +driver accesses the SPD and TSOD over the +.Xr smbus 4 . +.Pp +The data is reported via a +.Xr sysctl 8 +interface; all values are read-only: +.Bl -tag -width "dev.jedec_dimm.X.capacity" +.It Va dev.jedec_dimm.X.%desc +a string description of the DIMM, including TSOD and slotid info if present. +.It Va dev.jedec_dimm.X.capacity +the DIMM's memory capacity, in megabytes +.It Va dev.jedec_dimm.X.part +the manufacturer's part number of the DIMM +.It Va dev.jedec_dimm.X.serial +the manufacturer's serial number of the DIMM +.It Va dev.jedec_dimm.X.slotid +a copy of the corresponding hint, if set +.It Va dev.jedec_dimm.X.temp +if a TSOD is present, the reported temperature +.It Va dev.jedec_dimm.X.type +the DIMM type (DDR3 or DDR4) +.El +.Pp +These values are configurable for +.Nm +via +.Xr device.hints 5 : +.Bl -tag -width "hint.jedec_dimm.X.slotid" +.It Va hint.jedec_dimm.X.at +the +.Xr smbus 4 +to which the DIMM is connected +.It Va hint.jedec_dimm.X.addr +the SMBus address of the SPD. +JEDEC specifies that the four most-significant bits of the address are the +.Dq Device Type Identifier +(DTI), and that the DTI of the SPD is 0xa. +Since the least-significant bit of an SMBus address is the read/write bit, and +is always written as 0, that means the four least-significant bits of the +address must be even. +.It Va hint.jedec_dimm.X.slotid +optional slot identifier. +If populated with the DIMM slot name silkscreened on the motherboard, this +provides a mapping between the DIMM slot name and the DIMM serial number. +That mapping is useful for detailed asset tracking, and makes it easier to +physically locate a specific DIMM when doing a replacement. +This is useful when assembling multiple identical systems, as might be done by +a system vendor. +The mapping between bus/address and DIMM slot must first be determined, either +through motherboard documentation or trial-and-error. +.El +.Pp +If the DIMMs are on an I2C bus behind an +.Xr iicbus 4 +controller, then the +.Xr iicsmb 4 +bridge driver can be used to attach the +.Xr smbus 4 . +.Sh EXAMPLES +Consider two DDR4 DIMMs with the following hints: +.Bd -literal -offset indent +hint.jedec_dimm.0.at="smbus0" +hint.jedec_dimm.0.addr="0xa0" +hint.jedec_dimm.0.slotid="A1" + +hint.jedec_dimm.6.at="smbus1" +hint.jedec_dimm.6.addr="0xa8" +.Ed +.Pp +Their +.Xr sysctl 8 +output (sorted): +.Bd -literal -offset indent +dev.jedec_dimm.0.%desc: DDR4 DIMM w/ Atmel TSOD (A1) +dev.jedec_dimm.0.%driver: jedec_dimm +dev.jedec_dimm.0.%location: addr=0xa0 +dev.jedec_dimm.0.%parent: smbus0 +dev.jedec_dimm.0.%pnpinfo: +dev.jedec_dimm.0.capacity: 16384 +dev.jedec_dimm.0.part: 36ASF2G72PZ-2G1A2 +dev.jedec_dimm.0.serial: 0ea815de +dev.jedec_dimm.0.slotid: A1 +dev.jedec_dimm.0.temp: 32.7C +dev.jedec_dimm.0.type: DDR4 + +dev.jedec_dimm.6.%desc: DDR4 DIMM w/ TSE2004av compliant TSOD +dev.jedec_dimm.6.%driver: jedec_dimm +dev.jedec_dimm.6.%location: addr=0xa8 +dev.jedec_dimm.6.%parent: smbus1 +dev.jedec_dimm.6.%pnpinfo: +dev.jedec_dimm.6.capacity: 8192 +dev.jedec_dimm.6.part: VRA9MR8B2H1603 +dev.jedec_dimm.6.serial: 0c4c46ad +dev.jedec_dimm.6.temp: 43.1C +dev.jedec_dimm.6.type: DDR4 +.Ed +.Sh COMPATIBILITY +Hints for +.Xr jedec_ts 4 +can be mechanically converted for use with +.Nm . +Two changes are required: +.Bl -enum +.It +In all +.Xr jedec_ts 4 +hints, replace +.Dq jedec_ts +with +.Dq jedec_dimm +.It +In +.Xr jedec_ts 4 +.Dq addr +hints, replace the TSOD DTI +.Dq 0x3 +with the SPD DTI +.Dq 0xa +.El +.Pp +The following +.Xr sed 1 +script will perform the necessary changes: +.Bd -literal -offset indent +sed -i ".old" -e 's/jedec_ts/jedec_dimm/' \\ + -e '/jedec_dimm/s/addr="0x3/addr="0xa/' /boot/device.hints +.Ed +.Sh SEE ALSO +.Xr iicbus 4 , +.Xr iicsmb 4 , +.Xr jedec_ts 4 , +.Xr smbus 4 , +.Xr sysctl 8 +.Sh STANDARDS +.Rs +(DDR3 SPD) +.%A JEDEC +.%T Standard 21-C, Annex K +.Re +.Pp +.Rs +(DDR3 TSOD) +.%A JEDEC +.%T Standard 21-C, TSE2002av +.Re +.Pp +.Rs +(DDR4 SPD) +.%A JEDEC +.%T Standard 21-C, Annex L +.Re +.Pp +.Rs +(DDR4 TSOD) +.%A JEDEC +.%T Standard 21-C, TSE2004av +.Re +.Sh HISTORY +The +.Nm +driver first appeared in +.Fx 12.0 . +.Sh AUTHORS +.An -nosplit +The +.Nm +driver and this manual page were written by +.An Ravi Pokala Aq Mt rpokala@freebsd.org . +They are both based in part on the +.Xr jedec_ts 4 +driver and manual page, written by +.An Andriy Gapon Aq Mt avg@FreeBSD.org . Modified: head/sys/conf/NOTES ============================================================================== --- head/sys/conf/NOTES Thu Feb 22 23:06:39 2018 (r329842) +++ head/sys/conf/NOTES Thu Feb 22 23:18:46 2018 (r329843) @@ -2490,8 +2490,10 @@ device smb # SMBus peripheral devices # +# jedec_dimm Asset and temperature reporting for DDR3 and DDR4 DIMMs # jedec_ts Temperature Sensor compliant with JEDEC Standard 21-C # +device jedec_dimm device jedec_ts # I2C Bus Modified: head/sys/conf/files ============================================================================== --- head/sys/conf/files Thu Feb 22 23:06:39 2018 (r329842) +++ head/sys/conf/files Thu Feb 22 23:18:46 2018 (r329843) @@ -2274,6 +2274,7 @@ dev/ixgbe/ixgbe_dcb_82598.c optional ix inet | ixv ine compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_dcb_82599.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" +dev/jedec_dimm/jedec_dimm.c optional jedec_dimm smbus dev/jedec_ts/jedec_ts.c optional jedec_ts smbus dev/jme/if_jme.c optional jme pci dev/joy/joy.c optional joy Added: head/sys/dev/jedec_dimm/jedec_dimm.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/jedec_dimm/jedec_dimm.c Thu Feb 22 23:18:46 2018 (r329843) @@ -0,0 +1,1010 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Authors: Ravi Pokala (rpokala@freebsd.org), Andriy Gapon (avg@FreeBSD.org) + * + * Copyright (c) 2016 Andriy Gapon <avg@FreeBSD.org> + * Copyright (c) 2018 Panasas + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * This driver is a super-set of jedec_ts(4), and most of the code for reading + * and reporting the temperature is either based on that driver, or copied + * from it verbatim. + */ + +#include <sys/param.h> +#include <sys/kernel.h> +#include <sys/bus.h> +#include <sys/endian.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/sysctl.h> +#include <sys/systm.h> + +#include <dev/jedec_dimm/jedec_dimm.h> +#include <dev/smbus/smbconf.h> +#include <dev/smbus/smbus.h> + +#include "smbus_if.h" + +struct jedec_dimm_softc { + device_t dev; + device_t smbus; + uint8_t spd_addr; /* SMBus address of the SPD EEPROM. */ + uint8_t tsod_addr; /* Address of the Thermal Sensor On DIMM */ + uint32_t capacity_mb; + char type_str[5]; + char part_str[21]; /* 18 (DDR3) or 20 (DDR4) chars, plus terminator */ + char serial_str[9]; /* 4 bytes = 8 nybble characters, plus terminator */ + char *slotid_str; /* Optional DIMM slot identifier (silkscreen) */ +}; + +/* General Thermal Sensor on DIMM (TSOD) identification notes. + * + * The JEDEC TSE2004av specification defines the device ID that all compliant + * devices should use, but very few do in practice. Maybe that's because the + * earlier TSE2002av specification was rather vague about that. + * Rare examples are IDT TSE2004GB2B0 and Atmel AT30TSE004A, not sure if + * they are TSE2004av compliant by design or by accident. + * Also, the specification mandates that PCI SIG manufacturer IDs are to be + * used, but in practice the JEDEC manufacturer IDs are often used. + */ +const struct jedec_dimm_tsod_dev { + uint16_t vendor_id; + uint8_t device_id; + const char *description; +} known_tsod_devices[] = { + /* Analog Devices ADT7408. + * http://www.analog.com/media/en/technical-documentation/data-sheets/ADT7408.pdf + */ + { 0x11d4, 0x08, "Analog Devices TSOD" }, + + /* Atmel AT30TSE002B, AT30TSE004A. + * http://www.atmel.com/images/doc8711.pdf + * http://www.atmel.com/images/atmel-8868-dts-at30tse004a-datasheet.pdf + * Note how one chip uses the JEDEC Manufacturer ID while the other + * uses the PCI SIG one. + */ + { 0x001f, 0x82, "Atmel TSOD" }, + { 0x1114, 0x22, "Atmel TSOD" }, + + /* Integrated Device Technology (IDT) TS3000B3A, TSE2002B3C, + * TSE2004GB2B0 chips and their variants. + * http://www.idt.com/sites/default/files/documents/IDT_TSE2002B3C_DST_20100512_120303152056.pdf + * http://www.idt.com/sites/default/files/documents/IDT_TS3000B3A_DST_20101129_120303152013.pdf + * https://www.idt.com/document/dst/tse2004gb2b0-datasheet + */ + { 0x00b3, 0x29, "IDT TSOD" }, + { 0x00b3, 0x22, "IDT TSOD" }, + + /* Maxim Integrated MAX6604. + * Different document revisions specify different Device IDs. + * Document 19-3837; Rev 0; 10/05 has 0x3e00 while + * 19-3837; Rev 3; 10/11 has 0x5400. + * http://datasheets.maximintegrated.com/en/ds/MAX6604.pdf + */ + { 0x004d, 0x3e, "Maxim Integrated TSOD" }, + { 0x004d, 0x54, "Maxim Integrated TSOD" }, + + /* Microchip Technology MCP9805, MCP9843, MCP98242, MCP98243 + * and their variants. + * http://ww1.microchip.com/downloads/en/DeviceDoc/21977b.pdf + * Microchip Technology EMC1501. + * http://ww1.microchip.com/downloads/en/DeviceDoc/00001605A.pdf + */ + { 0x0054, 0x00, "Microchip TSOD" }, + { 0x0054, 0x20, "Microchip TSOD" }, + { 0x0054, 0x21, "Microchip TSOD" }, + { 0x1055, 0x08, "Microchip TSOD" }, + + /* NXP Semiconductors SE97 and SE98. + * http://www.nxp.com/docs/en/data-sheet/SE97B.pdf + */ + { 0x1131, 0xa1, "NXP TSOD" }, + { 0x1131, 0xa2, "NXP TSOD" }, + + /* ON Semiconductor CAT34TS02 revisions B and C, CAT6095 and compatible. + * https://www.onsemi.com/pub/Collateral/CAT34TS02-D.PDF + * http://www.onsemi.com/pub/Collateral/CAT6095-D.PDF + */ + { 0x1b09, 0x08, "ON Semiconductor TSOD" }, + { 0x1b09, 0x0a, "ON Semiconductor TSOD" }, + + /* ST[Microelectronics] STTS424E02, STTS2002 and others. + * http://www.st.com/resource/en/datasheet/cd00157558.pdf + * http://www.st.com/resource/en/datasheet/stts2002.pdf + */ + { 0x104a, 0x00, "ST Microelectronics TSOD" }, + { 0x104a, 0x03, "ST Microelectronics TSOD" }, +}; + +static int jedec_dimm_attach(device_t dev); + +static int jedec_dimm_capacity(struct jedec_dimm_softc *sc, enum dram_type type, + uint32_t *capacity_mb); + +static int jedec_dimm_detach(device_t dev); + +static int jedec_dimm_dump(struct jedec_dimm_softc *sc, enum dram_type type); + +static int jedec_dimm_field_to_str(struct jedec_dimm_softc *sc, char *dst, + size_t dstsz, uint16_t offset, uint16_t len, bool ascii); + +static int jedec_dimm_probe(device_t dev); + +static int jedec_dimm_readw_be(struct jedec_dimm_softc *sc, uint8_t reg, + uint16_t *val); + +static int jedec_dimm_temp_sysctl(SYSCTL_HANDLER_ARGS); + +static const char *jedec_dimm_tsod_match(uint16_t vid, uint16_t did); + + +/** + * device_attach() method. Read the DRAM type, use that to determine the offsets + * and lengths of the asset string fields. Calculate the capacity. If a TSOD is + * present, figure out exactly what it is, and update the device description. + * If all of that was successful, create the sysctls for the DIMM. If an + * optional slotid has been hinted, create a sysctl for that too. + * + * @author rpokala + * + * @param[in,out] dev + * Device being attached. + */ +static int +jedec_dimm_attach(device_t dev) +{ + uint8_t byte; + uint16_t devid; + uint16_t partnum_len; + uint16_t partnum_offset; + uint16_t serial_len; + uint16_t serial_offset; + uint16_t tsod_present_offset; + uint16_t vendorid; + bool tsod_present; + int rc; + int new_desc_len; + enum dram_type type; + struct jedec_dimm_softc *sc; + struct sysctl_ctx_list *ctx; + struct sysctl_oid *oid; + struct sysctl_oid_list *children; + const char *tsod_match; + const char *slotid_str; + char *new_desc; + + sc = device_get_softc(dev); + ctx = device_get_sysctl_ctx(dev); + oid = device_get_sysctl_tree(dev); + children = SYSCTL_CHILDREN(oid); + + bzero(sc, sizeof(*sc)); + sc->dev = dev; + sc->smbus = device_get_parent(dev); + sc->spd_addr = smbus_get_addr(dev); + + /* The TSOD address has a different DTI from the SPD address, but shares + * the LSA bits. + */ + sc->tsod_addr = JEDEC_DTI_TSOD | (sc->spd_addr & 0x0f); + + /* Read the DRAM type, and set the various offsets and lengths. */ + rc = smbus_readb(sc->smbus, sc->spd_addr, SPD_OFFSET_DRAM_TYPE, &byte); + if (rc != 0) { + device_printf(dev, "failed to read dram_type: %d\n", rc); + goto out; + } + type = (enum dram_type) byte; + switch (type) { + case DRAM_TYPE_DDR3_SDRAM: + (void) snprintf(sc->type_str, sizeof(sc->type_str), "DDR3"); + partnum_len = SPD_LEN_DDR3_PARTNUM; + partnum_offset = SPD_OFFSET_DDR3_PARTNUM; + serial_len = SPD_LEN_DDR3_SERIAL; + serial_offset = SPD_OFFSET_DDR3_SERIAL; + tsod_present_offset = SPD_OFFSET_DDR3_TSOD_PRESENT; + break; + case DRAM_TYPE_DDR4_SDRAM: + (void) snprintf(sc->type_str, sizeof(sc->type_str), "DDR4"); + partnum_len = SPD_LEN_DDR4_PARTNUM; + partnum_offset = SPD_OFFSET_DDR4_PARTNUM; + serial_len = SPD_LEN_DDR4_SERIAL; + serial_offset = SPD_OFFSET_DDR4_SERIAL; + tsod_present_offset = SPD_OFFSET_DDR4_TSOD_PRESENT; + break; + default: + device_printf(dev, "unsupported dram_type 0x%02x\n", type); + rc = EINVAL; + goto out; + } + + if (bootverbose) { + /* bootverbose debuggery is best-effort, so ignore the rc. */ + (void) jedec_dimm_dump(sc, type); + } + + /* Read all the required info from the SPD. If any of it fails, error + * out without creating the sysctls. + */ + rc = jedec_dimm_capacity(sc, type, &sc->capacity_mb); + if (rc != 0) { + goto out; + } + + rc = jedec_dimm_field_to_str(sc, sc->part_str, sizeof(sc->part_str), + partnum_offset, partnum_len, true); + if (rc != 0) { + goto out; + } + + rc = jedec_dimm_field_to_str(sc, sc->serial_str, sizeof(sc->serial_str), + serial_offset, serial_len, false); + if (rc != 0) { + goto out; + } + + /* The MSBit of the TSOD-presence byte reports whether or not the TSOD + * is in fact present. If it is, read manufacturer and device info from + * it to confirm that it's a valid TSOD device. It's an error if any of + * those bytes are unreadable; it's not an error if the device is simply + * not known to us (tsod_match == NULL). + * While DDR3 and DDR4 don't explicitly require a TSOD, essentially all + * DDR3 and DDR4 DIMMs include one. + */ + rc = smbus_readb(sc->smbus, sc->spd_addr, tsod_present_offset, &byte); + if (rc != 0) { + device_printf(dev, "failed to read TSOD-present byte: %d\n", + rc); + goto out; + } + if (byte & 0x80) { + tsod_present = true; + rc = jedec_dimm_readw_be(sc, TSOD_REG_MANUFACTURER, &vendorid); + if (rc != 0) { + device_printf(dev, + "failed to read TSOD Manufacturer ID\n"); + goto out; + } + rc = jedec_dimm_readw_be(sc, TSOD_REG_DEV_REV, &devid); + if (rc != 0) { + device_printf(dev, "failed to read TSOD Device ID\n"); + goto out; + } + + tsod_match = jedec_dimm_tsod_match(vendorid, devid); + if (bootverbose) { + if (tsod_match == NULL) { + device_printf(dev, + "Unknown TSOD Manufacturer and Device IDs," + " 0x%x and 0x%x\n", vendorid, devid); + } else { + device_printf(dev, + "TSOD: %s\n", tsod_match); + } + } + } else { + tsod_match = NULL; + tsod_present = false; + } + + SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "type", + CTLFLAG_RD | CTLFLAG_MPSAFE, sc->type_str, 0, + "DIMM type"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "capacity", + CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, sc->capacity_mb, + "DIMM capacity (MB)"); + + SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "part", + CTLFLAG_RD | CTLFLAG_MPSAFE, sc->part_str, 0, + "DIMM Part Number"); + + SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "serial", + CTLFLAG_RD | CTLFLAG_MPSAFE, sc->serial_str, 0, + "DIMM Serial Number"); + + /* Create the temperature sysctl IFF the TSOD is present and valid */ + if (tsod_present && (tsod_match != NULL)) { + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temp", + CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, 0, + jedec_dimm_temp_sysctl, "IK", "DIMM temperature (deg C)"); + } + + /* If a "slotid" was hinted, add the sysctl for it. */ + if (resource_string_value(device_get_name(dev), device_get_unit(dev), + "slotid", &slotid_str) == 0) { + if (slotid_str != NULL) { + sc->slotid_str = malloc(strlen(slotid_str) + 1, + M_DEVBUF, (M_WAITOK | M_ZERO)); + strlcpy(sc->slotid_str, slotid_str, + sizeof(sc->slotid_str)); + SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "slotid", + CTLFLAG_RD | CTLFLAG_MPSAFE, sc->slotid_str, 0, + "DIMM Slot Identifier"); + } + } + + /* If a TSOD type string or a slotid are present, add them to the + * device description. + */ + if ((tsod_match != NULL) || (sc->slotid_str != NULL)) { + new_desc_len = strlen(device_get_desc(dev)); + if (tsod_match != NULL) { + new_desc_len += strlen(tsod_match); + new_desc_len += 4; /* " w/ " */ + } + if (sc->slotid_str != NULL) { + new_desc_len += strlen(sc->slotid_str); + new_desc_len += 3; /* space + parens */ + } + new_desc_len++; /* terminator */ + new_desc = malloc(new_desc_len, M_TEMP, (M_WAITOK | M_ZERO)); + (void) snprintf(new_desc, new_desc_len, "%s%s%s%s%s%s", + device_get_desc(dev), + (tsod_match ? " w/ " : ""), + (tsod_match ? tsod_match : ""), + (sc->slotid_str ? " (" : ""), + (sc->slotid_str ? sc->slotid_str : ""), + (sc->slotid_str ? ")" : "")); + device_set_desc_copy(dev, new_desc); + free(new_desc, M_TEMP); + } + +out: + return (rc); +} + +/** + * Calculate the capacity of a DIMM. Both DDR3 and DDR4 encode "geometry" + * information in various SPD bytes. The standards documents codify everything + * in look-up tables, but it's trivial to reverse-engineer the the formulas for + * most of them. Unless otherwise noted, the same formulas apply for both DDR3 + * and DDR4. The SPD offsets of where the data comes from are different between + * the two types, because having them be the same would be too easy. + * + * @author rpokala + * + * @param[in] sc + * Instance-specific context data + * + * @param[in] dram_type + * The locations of the data used to calculate the capacity depends on the + * type of the DIMM. + * + * @param[out] capacity_mb + * The calculated capacity, in MB + */ +static int +jedec_dimm_capacity(struct jedec_dimm_softc *sc, enum dram_type type, + uint32_t *capacity_mb) +{ + uint8_t bus_width_byte; + uint8_t bus_width_offset; + uint8_t dimm_ranks_byte; + uint8_t dimm_ranks_offset; + uint8_t sdram_capacity_byte; + uint8_t sdram_capacity_offset; + uint8_t sdram_pkg_type_byte; + uint8_t sdram_pkg_type_offset; + uint8_t sdram_width_byte; + uint8_t sdram_width_offset; + uint32_t bus_width; + uint32_t dimm_ranks; + uint32_t sdram_capacity; + uint32_t sdram_pkg_type; + uint32_t sdram_width; + int rc; + + switch (type) { + case DRAM_TYPE_DDR3_SDRAM: + bus_width_offset = SPD_OFFSET_DDR3_BUS_WIDTH; + dimm_ranks_offset = SPD_OFFSET_DDR3_DIMM_RANKS; + sdram_capacity_offset = SPD_OFFSET_DDR3_SDRAM_CAPACITY; + sdram_width_offset = SPD_OFFSET_DDR3_SDRAM_WIDTH; + break; + case DRAM_TYPE_DDR4_SDRAM: + bus_width_offset = SPD_OFFSET_DDR4_BUS_WIDTH; + dimm_ranks_offset = SPD_OFFSET_DDR4_DIMM_RANKS; + sdram_capacity_offset = SPD_OFFSET_DDR4_SDRAM_CAPACITY; + sdram_pkg_type_offset = SPD_OFFSET_DDR4_SDRAM_PKG_TYPE; + sdram_width_offset = SPD_OFFSET_DDR4_SDRAM_WIDTH; + break; + default: + device_printf(sc->dev, "unsupported dram_type 0x%02x\n", type); + rc = EINVAL; + goto out; + } + + rc = smbus_readb(sc->smbus, sc->spd_addr, bus_width_offset, + &bus_width_byte); + if (rc != 0) { + device_printf(sc->dev, "failed to read bus_width: %d\n", rc); + goto out; + } + + rc = smbus_readb(sc->smbus, sc->spd_addr, dimm_ranks_offset, + &dimm_ranks_byte); + if (rc != 0) { + device_printf(sc->dev, "failed to read dimm_ranks: %d\n", rc); + goto out; + } + + rc = smbus_readb(sc->smbus, sc->spd_addr, sdram_capacity_offset, + &sdram_capacity_byte); + if (rc != 0) { + device_printf(sc->dev, "failed to read sdram_capacity: %d\n", + rc); + goto out; + } + + rc = smbus_readb(sc->smbus, sc->spd_addr, sdram_width_offset, + &sdram_width_byte); + if (rc != 0) { + device_printf(sc->dev, "failed to read sdram_width: %d\n", rc); + goto out; + } + + /* The "SDRAM Package Type" is only needed for DDR4 DIMMs. */ + if (type == DRAM_TYPE_DDR4_SDRAM) { + rc = smbus_readb(sc->smbus, sc->spd_addr, sdram_pkg_type_offset, + &sdram_pkg_type_byte); + if (rc != 0) { + device_printf(sc->dev, + "failed to read sdram_pkg_type: %d\n", rc); + goto out; + } + } + + /* "Primary bus width, in bits" is in bits [2:0]. */ + bus_width_byte &= 0x07; + if (bus_width_byte <= 3) { + bus_width = 1 << bus_width_byte; + bus_width *= 8; + } else { + device_printf(sc->dev, "invalid bus width info\n"); + rc = EINVAL; + goto out; + } + + /* "Number of ranks per DIMM" is in bits [5:3]. Values 4-7 are only + * valid for DDR4. + */ + dimm_ranks_byte >>= 3; + dimm_ranks_byte &= 0x07; + if (dimm_ranks_byte <= 7) { + dimm_ranks = dimm_ranks_byte + 1; + } else { + device_printf(sc->dev, "invalid DIMM Rank info\n"); + rc = EINVAL; + goto out; + } + if ((dimm_ranks_byte >= 4) && (type != DRAM_TYPE_DDR4_SDRAM)) { + device_printf(sc->dev, "invalid DIMM Rank info\n"); + rc = EINVAL; + goto out; + } + + /* "Total SDRAM capacity per die, in Mb" is in bits [3:0]. There are two + * different formulas, for values 0-7 and for values 8-9. Also, values + * 7-9 are only valid for DDR4. + */ + sdram_capacity_byte &= 0x0f; + if (sdram_capacity_byte <= 7) { + sdram_capacity = 1 << sdram_capacity_byte; + sdram_capacity *= 256; + } else if (sdram_capacity_byte <= 9) { + sdram_capacity = 12 << (sdram_capacity_byte - 8); + sdram_capacity *= 1024; + } else { + device_printf(sc->dev, "invalid SDRAM capacity info\n"); + rc = EINVAL; + goto out; + } + if ((sdram_capacity_byte >= 7) && (type != DRAM_TYPE_DDR4_SDRAM)) { + device_printf(sc->dev, "invalid SDRAM capacity info\n"); + rc = EINVAL; + goto out; + } + + /* "SDRAM device width" is in bits [2:0]. */ + sdram_width_byte &= 0x7; + if (sdram_width_byte <= 3) { + sdram_width = 1 << sdram_width_byte; + sdram_width *= 4; + } else { + device_printf(sc->dev, "invalid SDRAM width info\n"); + rc = EINVAL; + goto out; + } + + /* DDR4 has something called "3DS", which is indicated by [1:0] = 2; + * when that is the case, the die count is encoded in [6:4], and + * dimm_ranks is multiplied by it. + */ + if ((type == DRAM_TYPE_DDR4_SDRAM) && + ((sdram_pkg_type_byte & 0x3) == 2)) { + sdram_pkg_type_byte >>= 4; + sdram_pkg_type_byte &= 0x07; + sdram_pkg_type = sdram_pkg_type_byte + 1; + dimm_ranks *= sdram_pkg_type; + } + + /* Finally, assemble the actual capacity. The formula is the same for + * both DDR3 and DDR4. + */ + *capacity_mb = sdram_capacity / 8 * bus_width / sdram_width * + dimm_ranks; + +out: + return (rc); +} + +/** + * device_detach() method. If we allocated sc->slotid_str, free it. Even if we + * didn't allocate, free it anyway; free(NULL) is safe. + * + * @author rpokala + * + * @param[in,out] dev + * Device being detached. + */ +static int +jedec_dimm_detach(device_t dev) +{ + struct jedec_dimm_softc *sc; + + sc = device_get_softc(dev); + free(sc->slotid_str, M_DEVBUF); + + return (0); +} + +/** + * Read and dump the entire SPD contents. + * + * @author rpokala + * + * @param[in] sc + * Instance-specific context data + * + * @param[in] dram_type + * The length of data which needs to be read and dumped differs based on + * the type of the DIMM. + */ +static int +jedec_dimm_dump(struct jedec_dimm_softc *sc, enum dram_type type) +{ + int i; + int rc; + bool page_changed; + uint8_t bytes[512]; + + page_changed = false; + + for (i = 0; i < 256; i++) { + rc = smbus_readb(sc->smbus, sc->spd_addr, i, &bytes[i]); + if (rc != 0) { + device_printf(sc->dev, + "unable to read page0:0x%02x: %d\n", i, rc); + goto out; + } + } + + /* The DDR4 SPD is 512 bytes, but SMBus only allows for 8-bit offsets. + * JEDEC gets around this by defining the "PAGE" DTI and LSAs. + */ + if (type == DRAM_TYPE_DDR4_SDRAM) { + page_changed = true; + rc = smbus_writeb(sc->smbus, + (JEDEC_DTI_PAGE | JEDEC_LSA_PAGE_SET1), 0, 0); + if (rc != 0) { + device_printf(sc->dev, "unable to change page: %d\n", + rc); + goto out; + } + /* Add 256 to the store location, because we're in the second + * page. + */ + for (i = 0; i < 256; i++) { + rc = smbus_readb(sc->smbus, sc->spd_addr, i, + &bytes[256 + i]); + if (rc != 0) { + device_printf(sc->dev, + "unable to read page1:0x%02x: %d\n", i, rc); + goto out; + } + } + } + + /* Display the data in a nice hexdump format, with byte offsets. */ + hexdump(bytes, (page_changed ? 512 : 256), NULL, 0); + +out: + if (page_changed) { + int rc2; + /* Switch back to page0 before returning. */ + rc2 = smbus_writeb(sc->smbus, + (JEDEC_DTI_PAGE | JEDEC_LSA_PAGE_SET0), 0, 0); + if (rc2 != 0) { + device_printf(sc->dev, "unable to restore page: %d\n", + rc2); + } + } + return (rc); +} + +/** + * Read a specified range of bytes from the SPD, convert them to a string, and + * store them in the provided buffer. Some SPD fields are space-padded ASCII, + * and some are just a string of bits that we want to convert to a hex string. + * + * @author rpokala + * + * @param[in] sc + * Instance-specific context data + * + * @param[out] dst + * The output buffer to populate + * + * @param[in] dstsz + * The size of the output buffer + * + * @param[in] offset + * The starting offset of the field within the SPD + * + * @param[in] len + * The length in bytes of the field within the SPD + * + * @param[in] ascii + * Is the field a sequence of ASCII characters? If not, it is binary data + * which should be converted to characters. + */ +static int +jedec_dimm_field_to_str(struct jedec_dimm_softc *sc, char *dst, size_t dstsz, + uint16_t offset, uint16_t len, bool ascii) +{ + uint8_t byte; + int i; + int rc; + bool page_changed; + + /* Change to the proper page. Offsets [0, 255] are in page0; offsets + * [256, 512] are in page1. + * + * *The page must be reset to page0 before returning.* + * + * For the page-change operation, only the DTI and LSA matter; the + * offset and write-value are ignored, so use just 0. + * + * Mercifully, JEDEC defined the fields such that none of them cross + * pages, so we don't need to worry about that complication. + */ + if (offset < JEDEC_SPD_PAGE_SIZE) { + page_changed = false; + } else if (offset < (2 * JEDEC_SPD_PAGE_SIZE)) { + page_changed = true; + rc = smbus_writeb(sc->smbus, + (JEDEC_DTI_PAGE | JEDEC_LSA_PAGE_SET1), 0, 0); + if (rc != 0) { + device_printf(sc->dev, + "unable to change page for offset 0x%04x: %d\n", + offset, rc); + } + /* Adjust the offset to account for the page change. */ + offset -= JEDEC_SPD_PAGE_SIZE; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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