Date: Tue, 17 Jun 2014 21:48:05 +0000 (UTC) From: Michael Tuexen <tuexen@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r267597 - in head/sys/arm: arm include Message-ID: <201406172148.s5HLm5mZ020696@svn.freebsd.org>
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Author: tuexen Date: Tue Jun 17 21:48:04 2014 New Revision: 267597 URL: http://svnweb.freebsd.org/changeset/base/267597 Log: Different versions of the ARM processor use different registers. Fix the code used on a Raspberry Pi. Reviewed by: markm@ Modified: head/sys/arm/arm/cpufunc.c head/sys/arm/include/cpu.h Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Tue Jun 17 21:09:03 2014 (r267596) +++ head/sys/arm/arm/cpufunc.c Tue Jun 17 21:48:04 2014 (r267597) @@ -1410,12 +1410,27 @@ cpu_scc_setup_ccnt(void) * you want! */ #ifdef _PMC_USER_READ_WRITE_ +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) + /* Use the Secure User and Non-secure Access Validation Control Register + * to allow userland access + */ + __asm volatile ("mcr p15, 0, %0, c15, c9, 0\n\t" + : + : "r"(0x00000001)); +#else /* Set PMUSERENR[0] to allow userland access */ __asm volatile ("mcr p15, 0, %0, c9, c14, 0\n\t" : : "r"(0x00000001)); #endif - /* Set up the PMCCNTR register as a cyclecounter: +#endif +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) + /* Set PMCR[2,0] to enable counters and reset CCNT */ + __asm volatile ("mcr p15, 0, %0, c15, c12, 0\n\t" + : + : "r"(0x00000005)); +#else + /* Set up the PMCCNTR register as a cyclecounter: * Set PMINTENCLR to 0xFFFFFFFF to block interrupts * Set PMCR[2,0] to enable counters and reset CCNT * Set PMCNTENSET to 0x80000000 to enable CCNT */ @@ -1426,6 +1441,7 @@ cpu_scc_setup_ccnt(void) : "r"(0xFFFFFFFF), "r"(0x00000005), "r"(0x80000000)); +#endif } #endif Modified: head/sys/arm/include/cpu.h ============================================================================== --- head/sys/arm/include/cpu.h Tue Jun 17 21:09:03 2014 (r267596) +++ head/sys/arm/include/cpu.h Tue Jun 17 21:48:04 2014 (r267597) @@ -25,7 +25,16 @@ get_cyclecount(void) * Read PMCCNTR. Curses! Its only 32 bits. * TODO: Fix this by catching overflow with interrupt? */ +/* The ARMv6 vs ARMv7 divide is going to need a better way of + * distinguishing between them. + */ +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) + /* ARMv6 - Earlier model SCCs */ + __asm __volatile("mrc p15, 0, %0, c15, c12, 1": "=r" (ccnt)); +#else + /* ARMv7 - Later model SCCs */ __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt)); +#endif ccnt64 = (uint64_t)ccnt; return (ccnt64); #else /* No performance counters, so use binuptime(9). This is slooooow */
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